A 2000 gate 10 n sec uncommitted logic array for telecommunications and computer applications

This paper discusses the development programme used for a VLSI bipolar process for the production of a 2000 Gate ULA.     

A 6K-gate CMOS gate array

Combining advanced 2 /spl mu/m CMOS technology with a newly developed double layer metallization technology, a high-performance 6K-gate CMOS gate array has been developed, featuring an inverter propagation delay time of 0.4 ns with a power dissipation of 10 /spl mu/W/MHz/stage. As a demonstration vehicle of the high-performance gate array, a 16 bit/spl times/16 bit parallel multiplier has been designed and fabricated in which 3365 basic cells are used. Typical multiplying time has been measured to be 130 ns at a 5 MHz clock rate with a power dissipation of 275 mW.     

Electrically reprogrammable ROM using N-channel memory transistors with floating gate

An electrically reprogrammable read-only-memory (REPROM) device, providing the fully decoded and on-board-writable functions, is described. The device consists of novel N-channel memory transistors with floating gate, non-volatile memory transistors, which enable electrically reprogramming operation. The memory transistor has been through more than 10⁷ rewrite cycles with no gain facto (β) decrease. The memory device has been processed by the flat-MOS and the Si-gate technologies. It has a 2048 bit memory capacity, organized as 256 words of 8 bits. The polycrystalline silicon floating gate is covered with vapor-deposited silicon nitride. This allows selective write and erase operation, giving the memory device a new bit-level reprogrammable function.     

A high-speed HEMT 1.5K gate array

A 1.5K-gate HEMT gate array has been developed, using a direct-coupled FET logic (DCFL) circuit. The chip, containing 1520 basic cells and 72 I/O cells, was 5.5 mm × 5.6 mm. The basic circuit was designed for two different threshold voltages for D-HEMT, in order to obtain high-speed performance both at room temperature and low temperature. Fully functional 8 × 8 bit parallel multipliers were fabricated on the gate-array chip. At room temperature a multiplication time of 3.7 ns including I/O buffer delay was achieved with power dissipation of 6.0 W at a supply voltage of 1.6 V, and at liquid-nitrogen temperature multiplication time was 3.1 ns where the supply voltage was 0.95 V and the power dissipation was 3.2 W.     

A 2500 gate bipolar macrocell array with 250 ps gate delay

An oxide-isolated walled-emitter structure has been developed to obtain high performance and high packing density. Using this process, a macrocell array having 2500 equivalent gates has been fabricated. A gate delay of 250 ps with a 1 mA current switch has been achieved. Special circuitry and macros have been incorporated on the LSI to enhance diagnostic capability at both the chip and the system levels. A pin array package with /spl theta//SUB JA//spl les/4/spl deg/C/W has been developed for the LSI chip.     

Automated gate array scaling

A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59 percent and the speed was increased more than 40 percent is illustrated.     

A flexible gate array architecture for high-speed and high-densityapplications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm² routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions     

Automated gate array scaling

A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.     

A 209 K-transistor ECL gate array with RAM

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V/sub cc/ power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.<>     

A triple-level wired 24K-gate CMOS gate array

A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.     

A ferroelectric memory-based secure dynamically programmable gate array

A nonvolatile ferroelectric memory-based eight-context dynamically programmable gate array (DPGA) enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories as well as the multicontext architecture. Since read and program sequences of configuration data loading from/to the DPGA are securely protected, unauthorized users cannot access the stored configuration data. The associated configuration memory consists of a SRAM-based six-transistor and 4-ferroelectric capacitor cell. The developed configuration memory achieves access time of 4ns, comparable to standard SRAM, which is 20 times faster than conventional ferroelectric memory; furthermore, it features a nondestructive read operation and a stable data recall scheme. The employed logic block circuit can effectively improve the available number of logic gates for the multicontext scheme with minimum area overhead. The prototype nonvolatile DPGA is fabricated in a 0.35-/spl mu/m CMOS with ferroelectric memory technology, and the implementation result of the Data Encryption Standard (DES) encryption/decryption functions on this DPGA presents proper operation up to 51 MHz at 3.3V. The nonvolatile storage of configuration memory is verified for power-supply voltage as low as 1.5 V at room temperature, which is the lowest operation voltage ever reported for PbZrTiO/sub 3/ (PZT)-based ferroelectric memories.     

User-programmable logic-chasing the gate array

Integrated circuits (ICs) come in a wide range of technologies, and can implement a bewildering variety of functions. For the systems builder, however, there is one aspect of an IC that, irrespective of technology or function, is likely to be of overriding importance: whether it can be bought as a standard `off-the-shelf' component, or whether it must be implemented as some form of ASIC (application-specific IC). Here, the author shows that to a degree, the various forms of user-programmable logic, e.g. PLAs (programmable logic array) and PALs (programmable array logic), can offer the best of both worlds, as they are effectively standard parts that can be customised without recourse to a lengthy and expensive factory-based procedure. He shows that due to current advances in semiconductor processing and device architecture, integration levels for user-programmable logic are rising dramatically, attaining levels of functionality that rival low- to medium-complexity gate arrays     

A gallium arsenide SDFL gate array with on-chip RAM

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.     

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.     

A CMOS gate array architecture for digital signal processingapplications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements     

A subnanosecond 8K-gate CMOS/SOS gate array

An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.     

从FPGA转换到门阵列

概述从FPGA或CPLD转换到门阵列是经济高效的，有时甚至只需几百个单元就能完成。这种转换设计需要什么后续技术？事实上转换到门阵列面临着电路的许多时序问题，这在FPGA设计中是不被注意的。本文论述了转换时遇到的几种由于设计不当所造成的时序问题，提出了避免这些问题的解决方案。同时对时序变化的部分原因及如何充分利用门阵列技术也进行了讨论。时序上的差异如果知道原始设计电路工作中每一步时序上的裕量，orbit半导体公司保证无论FPGA是否模拟过，都可以成功完成转换，其ATPG和结合缺省模拟分级确保了这一点。在转换完成前…     

High voltage floating gate array transistors

A new high voltage field-effect transistor is described. It features an array of uncontacted gate elements between the main gate and the drain which float so as to inhibit avalanche breakdown. Good agreement is obtained between model predictions and the performance of experimental devices fabricated in Si-TaSi/sub 2/ semiconductor-metal eutectic material. Transistors are demonstrated which hold off up to 1000 V, compared with the avalanche breakdown potential of 300 V or less expected for conventional devices made with similarly doped silicon.<>