Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

Design and Evaluation of Adiabatic Arithmetic Units

Adiabatic design is an attractive approach to reducingenergy consumption in VLSI circuits after exhausting the potentialof conventional energy-saving techniques. Despite the plethoraof adiabatic logic architectures that have been proposed in recentyears, several practical considerations in the design of nontrivialadiabatic circuits remain largely unexplored. Moreover, it isstill unclear whether adiabatic circuits of significant sizeand complexity can achieve substantial savings in energy dissipationover corresponding conventional designs. We recently designedseveral low-power arithmetic units using a dual-rail adiabaticlogic design style. We also designed static CMOS versions ofthese units and compared their energy dissipation with theircorresponding adiabatic designs. In this paper we describe ourimplementations, discuss architecture and logic-level issuesrelated to our adiabatic designs, and present the findings ofour empirical comparison. Our results suggest that adiabaticlogic can be used for the implementation of relatively complexVLSI circuits that dissipate significantly less energy than theircorresponding CMOS designs.     

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

Four-phase power clock generator for adiabatic logic circuits

A circuit for a four-phase trapezoidal power clock generator for adiabatic logic circuits realised with a double-well 0.25 μm CMOS technology and external inductors is proposed. The circuit, at a frequency of 7 MHz which is within the optimum frequency range for adiabatic circuits realised with 0.25 μm CMOS technology, has a conversion efficiency higher than 80%, and is robust with respect to parameter variations     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS     

Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces

The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect.     

On the design of low-voltage, low-power CMOS analog multipliers forRF applications

Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs     

具有交叉耦合结构的能量恢复型电路

本文从改变能量传输方式的观点出发讨论了ＣＭＯＳ电路中的绝热开关原理,并对如何实现恢复进行了分析。本言语重点对具有交 耦合结构的绝热电路的特性作了分析比较,并在ＰＡＬ电路诉基础上提出了一种与之相补的绝热电路－ＰＡＬ－１电路。     

A charge-trapping-based technique to design low-voltage BiCMOSlogic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

Precharged CMOS quaternary logic encoder-decoder circuits

Multiple-valued buses have been proposed as a way of overcoming the interconnection complexity of VLSI. In this paper we present efficient new encoder-decoder circuits for four-valued bus signalling in clocked CMOS VLSI systems. The important advantages of our designs are that they can be implemented by standard binary CMOS processes, and are considerably simpler than earlier designs. Furthermore, they have no static power dissipation. The circuits have been extensively simulated using SPICE and have been found to operate reliably.     

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.     

Low-voltage low-power improved linearity CMOS active resistor circuits

A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity, improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS (Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks. Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V. The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation of the model quality associated with the evolution toward latest nanotechnologies.     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2µm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

CMOS NAND and NOR Schmitt circuits

Original solutions of m-input NAND and NOR logic circuits with hysteresis in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of 2m + 1 paris of enhancement CMOS transistors. The hysteresis voltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis, even with very large process variations. The noise immunity is typically greater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given.     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2μm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.