A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.     

A unified reconfigurable CORDIC processor for floating-point arithmetic

ABSTRACT

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.     

Guest Editorial: Design and Implementation of DSP Systems

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 × 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm ² at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 μm CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for real-time image processing applications even for high-resolution images.     

Design and analysis of a dynamically reconfigurablethree-dimensional FPGA

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied     

Optically Immersed Bolometer IR Detectors Based on V<Subscript>2</Subscript>O<Subscript>5</Subscript> Thin Films with Polyimide Thermal Impedance Control Layer for Space Applications

Optically immersed bolometer IR detectors were fabricated using electron beam evaporated vanadium oxide as the sensing material. Spin-coated polyimide was used as medium to optically immerse the sensing element to the flat surface of a hemispherical germanium lens. This optical immersion layer also serves as the thermal impedance control layer and decides the performance of the devices in terms of responsivity and noise parameters. The devices were packaged in suitable electro-optical packages and the detector parameters were studied in detail. Thermal time constant varies from 0.57 to 6.0 ms and responsivity from 75 to 757 V W^?1 corresponding to polyimide thickness in the range 2 to 70 μm for a detector bias of 9 V in the wavelength region of 14–16 μm. Highest D* obtained was 1.2×10⁸ cmHz^1/2 W^?1. Noise equivalent temperature difference (NETD) of 20 mK was achieved for devices with polyimide thickness more than 32 μm. The figure of merit, NETD × τ product which describes trade-off between thermal time constant and sensitivity is also extensively studied for devices having different thickness of thermal impedance layers.     

Dynamic and Partial FPGA Exploitation

Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results     

Novel detector implementations for 3G LTE downlink and uplink

We summarize our recent state-of-the-art programmable and reconfigurable detector and QR decomposition (QRD) implementations targeting 3G long term evolution (LTE) downlink and uplink requirements. The downlink transmission is based on the orthogonal frequency division multiplexing, whereas the uplink transmission uses a single-carrier frequency-division multiple access. The downlink implementations are based on the programmable transport triggered architecture (TTA) which provides a flexible and energy efficient architecture template. In TTA detector implementation, the LTE detection rate requirements up to 20 MHz bandwidth and 4 × 4 antenna system with 64-QAM, are achieved by using 1–6 programmable cores in parallel. Each core runs at 277 MHz clock frequency and consumes 55.5–64.0 mW depending on the detector configuration. The downlink detector is based on the selective spanning with fast enumeration algorithm. The uplink field-programmable gate array (FPGA) detector implementation is targeted for 4 × 4 antenna system and 64-QAM achieving a detection rate requirement for 20 MHz bandwidth. The used FPGA board for uplink implementation is Xilinx Virtex-6 and the implementation has been carried out using Xilinx Vivado high level synthesis tool. Two different detector architectures are implemented. The first one achieves the detection rate requirement with a single processing block running at 231 MHz and the latter one with four blocks in parallel, each running at 247 MHz. The implemented detector is based on the K-best algorithm. A multiple-input multiple-output receiver requires QRD to produce valid inputs for the detector. In addition to detector implementations, QRD is also implemented on both TTA and FPGA. Modified Gram–Schmidt algorithm is used in both QRD implementations.     

An adaptive CFAR embedded system architecture for target detection

This paper presents field-programmable gate array (FPGA)-based novel forward and backward automatic censored cell algorithms using a Nios II core processor embedded on a Stratix II FPGA programmable device. These algorithms were recently presented for target detection in a nonhomogeneous environment, and they operate in a complementary manner to allow for high-resolution target detection with a time constraint fixed below 0.5 μs. The ACOSD-based constant false alarm rate detector does not require any prior information regarding the background environment and employs statistical analysis to dynamically calculate the threshold at which the ordered cells under investigation are accepted or rejected. The advantages of the proposed system lie in its simplicity and short processing time while maintaining a low development cost. For a reference window of 16 range cells, the experimental results obtained using the Stratix II development kit demonstrate that the proposed architecture works properly with a processing speed of 100 MHz and an overall detector execution time of 0.11 μs for each range cell. The designed hardware, which is an example of system-on-chip architecture, was physically realized in a Stratix II FPGA device, and the results are presented and discussed.     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.     

Input impedance matching optimization for adaptive low-power low-noise amplifiers

Portable and implantable devices with wireless connectivity generate a high demand for low-power RF circuits. Biasing transistors in the subthreshold region allows significant reduction of power consumption, but calls for effective design techniques to minimize performance tradeoffs. This paper addresses one of the challenges associated with subthreshold RF low-noise amplifier (LNA) design: The input impedance of the ubiquitous CMOS inductor-degenerated common-source LNA operated in the subthreshold region is analyzed. By taking the increased impact of larger parasitic capacitances in the subthreshold region into account, the proposed input impedance equations provide more precise S₁₁ prediction than the conventional approximation. In addition, a tuning method for the LNA’s input impedance is presented to guarantee matching in the presence of manufacturing process variations. This tuning is implemented with a programmable capacitance to allow for digitally-assisted calibration. A 2.4 GHz LNA was designed in 0.18 μm CMOS technology and post-layout simulations were performed with device corner models across temperature and supply voltages variations. With these variations and ±15 % source/gate inductor tolerance, the simulated S₁₁ (<?16 dB) of the tunable LNA is at least 8.5 dB better than for the identical reference design without tuning, while minimally affecting other performance parameters.     

Mixed signal SIMD processor array vision chip for real-time image processing

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.     

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

This paper presents the realization of a fault tolerance technique for a dynamically reconfigurable array of programmable cells. The three parts of the technique, fault detection, fault reconfiguration, and fault recovery, are implemented completely in hardware and form a self-contained system. Each of the parts can be exchanged by an alternative implementation without affecting the remaining parts too much, thus making the concept adaptable to different reconfigurable circuits. A hardware realization for the core mechanism is discussed and a prototypical design of a field-programmable gate array implementing the complete system is described. The technological development towards nanoscale feature sizes and the growing influence of deep-submicrometer effects will result in an inherent unreliability of the individual components of future circuit implementations and a higher vulnerability towards external influences. The technique discussed can be used to exploit dynamic reconfiguration capabilities of programmable arrays to alleviate system vulnerability towards these effects and thus to enhance their overall reliability.     

用Cyclone FPGA实现双倍数据率输入/输出接口

Cyclone系列芯片是美国Altera公司推出的低价格、高容量现场可编程门阵列器件(FPGA)，本文概速了他的主要特点，给出了其在与外部存储器接口时用到的双倍数据率输入／输出接口的设计方法和仿真结果，仿真结果表明，Cyclone系列芯片可有效的完成两倍数据率接口的功能．     

Testing configurable LUT-based FPGA's

We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work     

Design and Application of a 20K Gate Array

This paper describes the design and architecture of a novel VLSI gate array in CMOS technology and its application for a 3-bit error checking and correcting (ECC) unit. The cell rows of the master are arranged without intermediate channels for routing (``sea of gates'). This scheme can be utilized to build large macro cells and functional blocks like data paths or systolic array cells which are very area consuming to realize in conventional gate arrays. In addition, special pull-up/pull-down cells are included on the chip which can be used for data buses and timing circuits. The technology used is an advanced p-well CMOS process with 1.8-μm geometric channel lengths and a two-layer metallization. There are 260 programmable pads for input/output functions and 20 additional power pads (280 pads in total). Depending on the logic, circuits with up to 25 000 gates can be realized with this device.     

Characterization of a CMOS impedance tuning unit for DVB-H

The use of reconfigurable matching has become more and more desirable as mismatches between such interfaces as antenna and receiver increase. The present paper investigates reconfigurable matching by measurements of a CMOS Impedance Tuning Unit (ITU) designed for Digital Video Broadcasting for Handheld devices (DVB-H). The ITU consists of switched capacitors arranged in three capacitor banks, with inductors between them, thus creating a reconfigurable ladder matching network. It is demonstrated that any mismatch up to VSWR = 8 can be transformed to a mismatch better than VSWR = 2, that IIP2 = 7 dBm and IIP3 = 0.5 dBm, and that loss is 2.1 dB.     

Implementation of reconfigurable nth-order filter based on CCII

Topologies for realizing voltage and current mode reconfigurable nth-order filters based on the second-generation current conveyor (CCII) are assessed. The most compatible structure for field-programmable analog array is identified. A CCII adopting active current division networks are utilized for implementing the proposed filter leading to wide control of its coefficients. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 μm CMOS process.     

Real-time Doppler analysis of radar signals

Pulse Doppler radar Fourier analysis usually requires bulky and complex circuits to obtain a real-time implementation. The letter suggests the feasibility of a spectral analyser by means of commercial programmable gate array devices (PGAs) using Curtis and Wickenden's prime radix recursive algorithm transform' (PRAT). PRAT leads to simple and regular networks, which can be easily fitted in the proposed devices and then transferred to gate arrays.<>     

Automatic Target Recognition with Dynamic Reconfiguration

This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel level parallelism is exploited in an FPGA design for the bottleneck portion of the application. The implementation of this design achieved a speedup of 21 compared to running on the host processor. The paper then describes an FPGA resource manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can be reconfigured for other purposes. The IR ATR application was ported to work with the RM and has been shown to adapt to the amount of reconfigurable hardware that is available at the time the application is executed.