A 1.2-GHz Comparator With Adaptable Offset in 0.35- $mu$m CMOS

We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-$mu$m CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600$times$ and to accurately program a desired offset with maximum observed residual offset of 469 $mu$V and standard deviation of 199 $mu$ V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from ${-}1$ to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.      

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

An NMOS comparator for a bubble memory

A low-noise low-offset comparator was designed for a bubble memory system. The measured noise performance was 25 /spl mu/V rms or 13 nV//spl radic/Hz and the worst case offset voltage was determined to be 158 /spl mu/V. This results in a 1.30 mV comparator gray region.     

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

We introduce differential-mode hot electron injection for adapting and storing analog nonvolatile signed state variables. This approach is compatible with modern digital CMOS technologies and is readily extended to novel circuit applications. We highlight advantages of the technique by applying it to the design of an adaptive floating gate comparator (AFGC). This is the first use of this technique for adaptation in a nonlinear circuit. The AFGC computes appropriate voltages for locally adapting the input floating gate nodes to cancel offsets. The technique is amenable to both local and nonlocal adaptation which allows greater design flexibility. The AFGC has been fabricated in a commercially available 0.35 μm CMOS process. We experimentally demonstrate more than two orders of magnitude reduction in offset voltage: the mean offset is reduced by 416× relative to chips direct from the foundry and by 202× relative to UV-irradiated chips. We consider both static and dynamic adaptation and demonstrate that the the accuracy of dynamic offset cancellation is approximately two orders of magnitude better than static adaptation. In the presence of observed 8% injection mismatch, the AFGC robustly converges to within 728 μV of the desired input offset (mean offset −109 μV, standard deviation 379 μV). Adaptation occurs within milliseconds, with charge retention for more than one month, and variation of offset error with temperature of −15 μV/°C.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

Micropower high-performance SC building block for integrated low-level signal processing

A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.     

A high-voltage monolithic operational amplifier

An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.     

Practical charge-transfer amplifier design architectures for low-power flash A/D converters

Two improved charge-transfer amplifiers (CTAs), used as zero-static-bias comparator preamplifiers in flash analog-digital converters, are proposed. The first improvement eliminates the capacitive coupling at the amplifier input, reducing area and input capacitance. The second eliminates the need for a common-mode output reference voltage by deriving the common-mode output from a switched average of the power supplies. In the latter, nearly a full-scale input range is achieved while preserving the low-power low offset characteristics of earlier CTAs. Voltage comparator devices were constructed in 0.6-/spl mu/m double-poly, triple-metal CMOS to test the prototype CTA architectures. Input common-mode range and offset performance consistent with simulation data is demonstrated with a 10X reduction in input capacitance. Measured dynamic power dissipation on the order of 3-6 /spl mu/W/MSPS is observed. The experimental CTA preamplifiers occupy roughly 0.015 mm/sup 2/.     

A 16-bit low-voltage CMOS A/D converter

A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

A fast, latching comparator for 12 bit A/D applications

High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.     

A Micropower CMOS-Instrumentation Amplifier

A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-zero technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4-/spl mu/m double poly process has an offset (/spl tau/) of 370 /spl mu/V, an rms input referred integrated noise (0.5 -f/sub c//2) of 79 /spl mu/V, and consumes only 21 /spl mu/W (f/sub c/ = 8 kHz, V/sub DD/ = 3 V).     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

1-bit quantiser with rail to rail input range for sub-1 V /spl Delta//spl Sigma/ modulators

A new, fully differential comparator with rail to rail input range is presented. This comparator can be used as a 1-bit quantiser in sub-1 V /spl Delta//spl Sigma/ modulators. The quantiser is laid out in 0.18 /spl mu/m CMOS technology. The post-layout simulation results show that the quantiser is capable of working at 10 MHz with 10 /spl mu/V resolution. This quantiser is successfully used in 0.8 V first-order and second-order fully differential /spl Delta//spl Sigma/ modulators.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

Limits of temperature drift in noncompensated DC amplifiers

Temperature-stability limits of differential amplifiers consisting of two bipolar transistors mounted in tight thermal contact are discussed. No external temperature compensation or stabilization methods are provided. It is shown that the temperature drift of the input difference (offset) voltage is equal to about 3.3 to 3.9 /spl mu/V//spl deg/K per 1-mV difference (offset) voltage at room temperature (300/spl deg/K). This value seems to depend little on the transistor type used.     

一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0．35μm5VCMOS工艺实现一个输入电压2．5V、速度1MS／s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明：在5V供电电压下,速度可达20MHz,准确比较0．2mV电压,有效校准20mV输入失调,功耗约1mW。     

192 GHz push-push VCO in 0.13 /spl mu/m CMOS

A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 0.13 /spl mu/m CMOS logic process. The VCO can be tuned from 191.4 to 192.7 GHz. The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 1.5 V supply.