图像融合系统研究现状

图像融合是把同一场景从不同特性、不同时间、不同分辨率传感器获得的多幅图像综合成一幅图像的先进图像处理技术.阐述了实时图像处理系统的设计趋势,综述了图像融合系统的研究现状,指出了当前流行的设计方式.     

采用简化SIFT算法实现快速图像匹配

SIFT(Scale Invariant Feature Transform)算子因其良好的尺度、旋转、光照等不变特性而广泛应用于图像匹配中,但用128维向量来表征每个特征点降低了算法的实时性。为了提高匹配速度,介绍了一种基于SIFT的简化算法(SSIFT),采用基于圆形窗口的12维向量有效地表示一个特征点。实验结果显示,算法在保持较好匹配率的同时能降低时间复杂度,适合运用在对实时性要求较高的场合。     

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment     

REW软件——高分辨电子显微镜的像模拟与出射波函数重构的应用软件

通过像处理技术分析高分辨电子显微像有助于确定样品结构,提高显微镜的分辨率。本文开发的REW软件同时具有HRTEM像模拟与波函数重构的功能。用户可通过像模拟法来确定已知晶体的结构,另一方面,用户可利用系列离焦的HRTEM像重构样品的出射波函数,从而得到重要的相位信息并提高样品的分辨率。本文将简单介绍REW软件所运用的理论知识,并列举典型例子来描述REW软件的重要功能。     

Implementation of a bipolar real-time image signal processor-RISP-II

The high-speed digital image signal processor RISP-II, an improved version of the original real-time image signal processor (RISP) for gray-level image processing, is discussed. RISP-II has a microprogrammable architecture and a per-chip processing speed of 100 million instructions per second. Multichip processing has been realized by two added features: parallelism and pipelining. In the multichip mode its processing power can easily be increased. As a result, RISP-II is capable of real-time processing of the image data of a moving object. RISP-II, implemented in an advanced bipolar ECL technology, has integrated 20600 elements on a chip of 6/spl times/6 mm/SUP 2/. Its power dissipation is 1.6 W.     

DSP芯片在实时图像处理系统中的应用

在通用计算机上用软件实现图像处理，要占用CPU几乎全部的处理能力，且速度相对较慢。数字信号处理器(DSP)的可编程性和强大的处理能力使其可用于快速实现各种数字信号处理算法，在图像处理领域，尤其在实时图像处理系统中得到了广泛应用和发展。本文介绍了DSP芯片及其在实时图像处理系统中的开发、应用及发展方向。     

一种基于FPGA的彩色图像实时增强方法

彩色图像中包含了丰富的颜色信息,能够直观地感知世界,它使我们的工作生活更加便利。但是,由于一些恶劣环境的影响,彩色图像的成像会出现模糊、目标被淹没、对比度偏低等问题。针对此问题,本文设计了一款基于FPGA的嵌入式实时图像增强处理系统。并提出一种灰度值拉伸变换方法,将该方法直接对RGB色彩空间的R、G、B三分量进行增强处理,既增大了灰度值的变化范围提高人眼视觉效果,也避免了色彩空间转换带来的计算量及节省了处理时间满足了工程的实时性要求。目前该系统已在实际工程项目中应用,工程结果表明该系统工作稳定有效,能够有效解决工程中出现的光线条件差,低对比度情况下的彩色图像增强问题。     

图像处理在自动焊接中的应用

图像处理技术在自动焊接中的应用已引起广泛重视。本文以电池极板焊接为研究背景,在焊接中使用CCD相机摄取焊接图像,基于MATLAB软件,通过彩色图像处理,阈值分割后,将图像处理后结果输入到控制器中,控制器即可识别出焊接状态,并且可对检测出的漏焊点进行续焊,实现自动焊接智能化。实验结果表明,使用上述方法进行图像处理后的结果,可以实时传输到计算机高速缓存内,进行实时处理,提取特征信息,并作出在线判决,使得实现焊接过程质量实时传感与控制成为可能,在控制器中较好的显示了焊接状态。     

Minimal-bracketing sets for high-dynamic-range image capture

This paper considers the problem of high-dynamic-range (HDR) image capture using low-dynamic-range (LDR) cameras. We present three different minimal-bracketing algorithms for computing minimum-sized exposure sets bracketing of HDR scenes. Each algorithm is applicable to a different HDR-imaging scenario depending on the amount of target-scene-irradiance information and real-time image processing available at the time of image acquisition. We prove the optimality of each algorithm with respect to its ability to obtain a theoretically minimum-size bracketing set of exposures. We also provide closed-form expressions for computing minimal-bracketing exposure sets for two common types of HDR-imaging systems, those with geometrically varying and arithmetically varying exposure settings. We experimentally demonstrate the advantages of the proposed methods by capturing and processing multiple HDR scenes using minimal-bracketing and 1-stop bracketing methods. The results show that minimal-bracketing can be used to produce high-quality HDR images, while requiring only one third as many LDR images be acquired compared to 1-stop bracketing. We also perform a detailed SNR analysis that quantifies the tradeoff between signal-to-noise ratio and image-bracketing-set size.     

FAIR: a hardware architecture for real-time 3-D image registration

Mutual information-based image registration, shown to be effective in registering a range of medical images, is a computationally expensive process, with a typical execution time on the order of minutes on a modern single-processor computer. Accelerated execution of this process promises to enhance efficiency and therefore promote routine use of image registration clinically. This paper presents details of a hardware architecture for real-time three-dimensional (3-D) image registration. Real-time performance can be achieved by setting up a network of processing units, each with three independent memory buses: one each for the two image memories and one for the mutual histogram memory. Memory access parallelization and pipelining, by design, allow each processing unit to be 25 times faster than a processor with the same bus speed, when calculating mutual information using partial volume interpolation. Our architecture provides superior per-processor performance at a lower cost compared to a parallel supercomputer.     

基于VPX的多DSP+FPGA红外图像处理系统设计与实现

针对大面阵红外图像快速处理要求及模块化设计原则,本文采用了4片TI公司的DSP和1片Virtex7 FPGA设计了一个多DSP的红外图像实时处理系统,试验表明该系统适用于复杂图像处理算法的计算和实时图像中跟踪目标的实时处理.     

基于新遗传算法的Otsu图像阈值分割方法

最大类间方差（Otsu）图像分割法是常用的一种基于统计原理的图像阈值分割方法。为了改善Otsu耗时较多、分割的精度低、易产生图像误分割等不足,将猴王遗传算法与Otsu算法结合,运用猴王遗传算法的原理,寻找图像灰度的最大类间方差,即最佳阈值。结果表明,结合后的方法不仅提高了图像的分割质量、缩短了运算时间,而且非常适合图像的实时处理。     

A programmable image processing system using FPGAs

Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.     

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors     

基于FPGA的红外焦平面实时图像处理系统

针对红外焦平面阵列(IRFPA)实时图像处理系统中的重要环节——IRFPA的非均匀性校正和红外图像的增强,提出了以FPGA为核心的红外焦平面成像实时处理系统。该系统能够实时完成校正系数的计算、IRFPA非均匀性校正、红外图像的增强及视频合成等功能。在FPGA中采用了并行处理结构和流水线技术,使系统的处理速度高达50M×12 bit/s,特别适用于大面阵、高帧频IRFPA实时图像处理。仅用一片FPGA完成所有的处理功能,使整个系统结构简单、体积小、功耗小,便于小型化。     

High resolution image formation from low resolution frames using Delaunay triangulation

An algorithm based on spatial tessellation and approximation of each triangle patch in the Delaunay (1934) triangulation (with smoothness constraints) by a bivariate polynomial is advanced to construct a high resolution (HR) high quality image from a set of low resolution (LR) frames. The high resolution algorithm is accompanied by a site-insertion algorithm for update of the initial HR image with the availability of more LR frames till the desired image quality is attained. This algorithm, followed by post filtering, is suitable for real-time image sequence processing because of the fast expected (average) time construction of Delaunay triangulation and the local update feature.     

A real-time FPGA architecture for 3D reconstruction from integral images

In this paper, we present a hardware architecture for real-time three-dimensional (3D) surface model reconstruction from Integral Images (InIms). The proposed parallel digital system realizes a number of computational-heavy calculations in order to achieve real-time operation. The processing elements are deployed in a systolic architecture and operate on multiple image areas simultaneously. Moreover, memory organization allows random access to image data and copes with the increased processing throughput of the system. Operating results reveal that the proposed architecture is able to process 3D data at a real-time rate. The proposed system can handle large sized InIms in real time and outputs 3D scenes of enhanced depth and detailed texture, which apply to emerging 3D applications.     

基于FPGA的微光视频采集与预处理系统设计

针对当前微光视频图像采集与处理系统中数据处理量与系统实时性之间的矛盾,设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的实时信号采集与预处理系统。该系统以高性能Xilinx A7系列芯片为主控芯片,使用两片第二代双倍数据率同步动态随机存取存储器(Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM)作为核心存储器件,并定制超感光互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)传感镜头作为视频图像采集器件。完成系统的硬件设计之后,通过Xilinx Vivado平台以及Matlab进行软件系统的工程设计与仿真分析,实现了微光环境下视频图像的采集、存储、处理与显示的全过程。实验结果表明,该系统采集的微光视频图像实时性好、动态画面流畅。     

General logarithmic image processing convolution.

The logarithmic image processing model (LIP) is a robust mathematical framework, which, among other benefits, behaves invariantly to illumination changes. This paper presents, for the first time, two general formulations of the 2-D convolution of separable kernels under the LIP paradigm. Although both formulations are mathematically equivalent, one of them has been designed avoiding the operations which are computationally expensive in current computers. Therefore, this fast LIP convolution method allows to obtain significant speedups and is more adequate for real-time processing. In order to support these statements, some experimental results are shown in Section V.     

New real-time image processing system for IRFPA

Infraredfocal plane array(IRFPA) is a kind of infra-red detector array whichis sensitive toinfraredradiationandintegrated with signal processing circuits .The IRF-PAi maging systemhas advantages of si mple configura-tion,high reliability,high sensitivity …