TaN-TiN binary alloys and superlattices as diffusion barriers for copper interconnects

Binary alloys and superlattices of TaN-TiN thin films were grown on Si(100) substrates with a TiN buffer layer using pulsed laser deposition. A special target assembly was used to manipulate the concentrations of these binary component films. The 60% TaN resulted in a TaN (3 nm)/TiN (2 nm) superlattice, while 30% and 70% TaN generated uniform Ta_xTi_1−xN alloys. X-ray diffraction (XRD), transmission electron microscopy (TEM), and scanning transmission electron microscopy (STEM) confirmed the single-crystalline nature of these films. Four-point probe resistivity measurements suggest that these alloy and superlattice films have a lower resistivity than pure single-crystalline TaN films. The Cu-diffusion characteristic studies showed that these materials would have the potential as high-temperature diffusion barriers for Cu in ultra-large-scale integration technology.     

The effect of sputtered W-based carbide diffusion barriers on the thermal stability and void formation in copper thin films

The W-based diffusion barriers W, WC and WCN barriers were investigated for Cu metallization. The thermal stability of the W, WC and WCN barriers was compared by X-ray diffraction and four point probe. It shows comparable stability for the W and WC barriers while the ternary WCN barrier has superior performance. The agglomeration of the Cu films (100 nm) on these barriers is quite different. The formation of voids was observed for the annealed copper film on the WC or WCN barriers and the activation energy values determined from Kissinger equation are low comparing with Cu on W barrier. Twins were also observed in the as-deposited and annealed Cu films on the WC and WCN barriers. The twin formation and its correlation with void formation for Cu films onto the C-containing diffusion barrier were discussed through the stress relaxation and stress-induced vacancy migration mechanism.     

Structural and electrical characterization of CoNiO monolayer as copper diffusion barrier in integrated circuits

Diffusion barrier properties of CoNiO monolayer, deposited by Langmuir Blodgett (LB) technique, were studied against the diffusion of copper through SiO₂. Cu/CoNiO/SiO₂/Si and Cu/SiO₂/Si test structures were prepared and compared for this purpose. These test structures were annealed at temperatures starting from 100 °C up to 650 °C in vacuum. Samples were characterized using Energy Dispersive X-ray Spectroscopy (EDS), Atomic force microscopy (AFM), X-ray diffraction (XRD), scanning electron microscope (SEM), four probe resistivity measurement, Capacitance-Voltage (C‒V), Current-Voltage (I‒V) characterization techniques. EDS and AFM confirmed the composition and structure of the deposited monolayer. Thermal stability was studied using X-ray diffraction (XRD), Scanning Electron Microscope (SEM) and four probe techniques. Results indicated that structure with barrier was stable up to 600 °C whereas its counterpart could sustain only up to 300 °C. Sheet resistance of Cu/SiO₂/Si structure starts increasing at 300 °C and that of Cu/CoNiO/SiO₂/Si test structure was almost unchanged up to 600 °C in. SEM analysis of samples annealed at different temperatures also confirmed the XRD and four probe results. Biased Thermal Stress (BTS) was applied to the samples and its effect was observed using C‒V analysis. C‒V curves showed that in the presence of CoNiO barrier layer there was no shift in the C‒V curve even after 120 min of BTS while in the absence of barrier there was a significant shift in the C‒V curve even after 30 min of BTS. Leakage current density (j_L) was plotted against the BTS duration under same BTS conditions. It was found that the Cu/CoNiO/SiO₂/Si stack could survive about two times more than the Cu/SiO₂/Si stack.     

Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation stress testing

We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current–voltage (I–V) curve measured at the elevated stress temperature, during potential‐induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum‐power temperature translation methods found in the literature. For the first method, which is based on the maximum‐power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two‐diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large‐scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum‐power temperature translation method, by taking advantage of the near‐linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Copyright © 2015 John Wiley & Sons, Ltd.