USB设备控制器端点缓冲区的优化设计

讨论使用异步FIFO作为USB端点缓冲区的设计方案.根据USB四种传输类型的特点,灵活地设计了不同端点缓冲区的实现方案.特别是针对控制端点传输的特殊性,提出一种新型的双向FIFO设计.与传统结构相比,该方案在保证控制传输的功能下电路的实现面积减小了近1/2.对于其他类型端点的设计方案,为了保证传输速度,使用了双缓冲FIFO的结构,有效地保证了接口的传输速度.最后给出了电路的ASIC的实现结果.     

循环缓冲机制在DSP异步数据访问中的应用

目前,数字信号处理器(DSP)芯片被广泛应用于声频信号处理系统中,各种数据接口日趋复杂。在这些嵌入式程序设计中,经常需要在多个中断服务程序之间进行数据交互,然而在很多系统中这些中断的时钟源并不一致。由于时钟抖动使得这些中断的相对到来时刻不是固定的,导致数据传输的不可靠性。提出通过建立循环缓冲区来协调系统中异步数据的传输。该机制通过合理地选择循环缓冲区的长度,使得数据的读操作和写操作之间具有一定的延时,从而缓解了时钟抖动导致的数据丢失或覆盖问题。实验验证了该方法的有效性和稳健性。     

基于GALS的SOC异步接口研究

基于MOUSETRAP异步流水线结构提出了一种全局异步局部同步方式下的片上系统的异步互连接口架构.为实现异步接口电路的低功耗,对其进行了晶体管级的功耗优化设计.同时,利用基于多级供电电压控制下的延时可调机制,以缓解该异步互连中匹配延时链设计困难带来工艺可移植性差的问题.该接口适用于对数据传输率和功耗有较高要求的多电压供电片上系统设计.     

双轨异步环路收发器设计

设计实现了一种新型多点连接的GALS异步互连接口.该接口采用旁路式结构,避免了现有的馈通式结构接口由于时钟频繁启停造成的时间利用率和能量利用率低下的缺陷.该接口的数据传输采用四相双轨握手协议,简化了握手过程,进一步提高了速度.在TSMC0.25μm的工艺下,该接口的最高传输频率可以达到603.7MHz.该接口适用于对数据传输速度要求较高的SOC设计.     

基于FPGA的液晶显示接口设计

为了解决CPU处理速度快,而液晶显示模块处理速度慢的矛盾,提高系统的运行的速度.利用FPGA以及异步FIFO的IP核实现液晶显示接口,在CPU和液晶模块之间建立一个FIFO缓冲区.同时根据液晶模块控制的流程设计了一个有限状态机,对液晶的数据命令信号进行控制,满足液晶模块读写的时序,实现了液晶模块控制命令以及显示数据的正确写入.测试结果表明,整个接口设计实现方式简单,可靠.     

PowerPC8270数据处理模块的异步总线接口设计

针对嵌入式计算机系统中的60X总线应用,文章提出了一种PowerPC8270数据处理模块的异步总线接口设计。文章先介绍了该模块的系统结构,然后主要介绍了PowerPC8270处理器的异步总线接口硬件结构和软件设计思想,支持外部设备的灵活访问。     

基于FPGA的异步FIR滤波器接口电路设计

介绍了基于四相单轨握手协议的异步FIR滤波器接口电路的设计。分析了异步接口电路互联模型及原理,提出了一种基于存储器和状态机实现异步握手接口电路的全新方案,实现了FIR滤波器功能和异步接口控制功能。对设计进行了波形仿真及结果分析,验证了设计方案的可行性。     

网络协议缓冲区—队列层次接口监督函数的实现

本文提出了一种新型计算机网络协议层次间的信息接口—缓冲区—队列接口的实现方法，给出了实现这种接口监督函数的PASCAL算法，由这些算法实现的监督函数可有效地对网络的缓冲区—队列接口进行调度管理，实现网络协议层次间的优化信息流动。     

异步Viterbi解码器同步接口的设计

提出了一种利用异步 FIFO ( First In First Out)连接异步逻辑电路与同步逻辑电路的方法 ,并设计实现了相应的异步 FIFO电路 ,作为连接异步 viterbi解码器和其他同步逻辑电路的同步接口。对异步 FIFO的级数与异步 viterbi解码器内部的时序关系进行了分析。用逻辑仿真的动态时序分析表明 ,当同步电路时钟的周期大于 130 ns时 ,具有同步接口的异步 viterbi解码器可以与同步电路正常协同工作。具有简单接口电路的异步解码器 ,既能发挥异步电路功率效率高的优点 ,而且能嵌入同步电路系统     

基于双缓冲和FPGA的RS422接口电路设计

RS422异步串行通信技术广泛应用于机载计算机实时控制系统,提高了飞机的可维护性和可扩展性。设计了一种双缓冲模式RS422接口电路,采用通用的异步串行通信控制器。阐述了机载计算机RS422的通信协议,详细介绍了双缓冲策略。应用结果表明,该系统数据缓存能力强,提高了数据传输速度,使用简单。     

一种基于标准逻辑单元的GALS异步封装电路

基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计.由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性.     

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.     

一种基于电压岛的片上网络低功耗设计

功耗问题一直是片上网络设计中最为关心的问题之一.基于全局异步局部同步(GALS)的电压岛(VFI)机制的引入不但提供了极大地降低片上功耗的可能,也解决了片上单时钟传输的瓶颈问题.本文改善了现有的两种电压岛划分、核映射及路由分配方法,提出了一种更优的综合解决方案,并进行了验证.仿真结果显示,本文的方案可以显著降低系统功耗,同时提高了片上网络性能.     

High Rate Data Synchronization in GALS SoCs

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner     

Core与总线系统的异步通信接口设计

文章基于GALS（Globally Asynchronous Locally Synchronous）设计理念，提出一个Core的异步接口设计模型：门控时钟停Core机制、握手机制、电平转脉冲逻辑等构成的异步控制信号处理模型：异步FIFO和双FIFO结构构成的异步数据处理模型。此结构允许Core和总线系统在完全异步的时钟域上工作。FPGA验证结果表明．该模型能正确地实现两者问的信号同步，并能满足具体应用的带宽需求。     

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.     

From synchronous to GALS: A new architecture for FPGAs

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.     

一种便携式数据采集终端的设计与实现

为满足移动数据采集及固定设备长时间存储需要,设计一种通用型可视化便携式数据采集终端系统,该系统由单芯片U盘读写方案(PB375A)、现场可编程门阵列(FPGA)及单片机构成.他提供通用异步接收/发送装置(Universal asynchronous receiver/transmitter,UART)、串行外围设备两种输入接口(Serial peripheral interface,SPI),以及U盘、SD卡两种存储接口.实验结果表明,系统的平均存储速率达到100 Kbps,能实现用户可视化操作,稳定性好,携带方便.     

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for processing computationally-intensive and energy-constrained workloads. The GALS methodology simplifies clock tree design, provides opportunities to use clock and voltage scaling jointly in system submodules to achieve high energy efficiencies, and can also result in easily scalable clocking systems. However, its use typically also introduces performance penalties due to additional communication latency between clock domains. We show that GALS chip multiprocessors (CMPs) with large inter-processor first-inputs–first-outputs (FIFOs) buffers can inherently hide much of the GALS performance penalty while executing applications that have been mapped with few communication loops. In fact, the penalty can be driven to zero with sufficiently large FIFOs and the removal of multiple-loop communication links. We present an example mesh-connected GALS chip multiprocessor and show it has a less than 1% performance (throughput) reduction on average compared to the corresponding synchronous system for many DSP workloads. Furthermore, adaptive clock and voltage scaling for each processor provides an approximately 40% power savings without any performance reduction. These results compare favorably with the GALS uniprocessor, which compared to the corresponding synchronous uniprocessor, has a reported greater than 10% performance (throughput) reduction and an energy savings of approximately 25% using dynamic clock and voltage scaling for many general purpose applications.      

岸船数据传输问题分析和解决

针对岸船间采用多业务交换机(MSS)和双向不对称卫星信道传输数据的问题,通过深入分析研究MSS的接口和协议特性,提出了岸船之间MSS双向不对称中继组网、单向数据传输和低速异步数据传输等特殊应用的解决方案,并通过测试验证了方案的可行性。实现了岸船之间利用一条双向不对称卫星信道传输IP数据、话音、单向/双向电路数据、单向视频和异步数据等综合业务的需求,为工程实施提供了技术指导和依据。