Low-power equalizer architectures for high speed modems

In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit     

基于硬件构件的嵌入式系统低功耗研究

降低系统功耗不仅要考虑硬件方面的因素,同时也要分析因软件引起的功耗。为了降低系统整体功耗,首先需要明确影响系统功耗的软硬件因素。在硬件方面,通过对硬件构件进行选择、设计和整合等方法降低功耗;软件方面则是重点优化与功耗密切相关的要素,如算法、指令与方法等。这些因素往往是相互制约、相互影响的。设计一个成功的低功耗系统,需要通过分析与实验,明确一个以硬件构件为思想的嵌入式系统低功耗设计时所需考虑的一些问题。     

低功耗编译技术综述

功耗问题已经成为制约电子系统发展的重要因素.功耗是由硬件在运行软件时产生的,软件的数据存取和指令执行都会使硬件产生功耗.编译器可以通过适当的调度优化,改变软件在硬件上的运行轨迹,使得硬件执行某一个程序时的功耗变小.本文从如何对软件的功耗进行评估和如何实现低功耗的编译两大方面对低功耗编译的相关研究进行了广泛介绍,着重评述了专门的低功耗编译技术.最后对当前低功耗编译存在的问题做了分析,给出了对于低功耗编译新方向的预测.     

Transmeta's magic show [microprocessor chips]

It took Transmeta engineers $100 million, five years of secret toil, and a little magic to create fast low-power chips that turn into x86s in a microsecond. Transmeta Corporation's Crusoe chips look nothing like Intel's Pentium processors. They do not even have a logic gate in common. They are smaller, consume between one-third and one-thirtieth the power (depending on the application), and implement none of the same instructions in hardware. However the Crusoe microprocessors can run the same software that runs on IBM PC-compatible personal computers with Pentium chips-for instance, Microsoft Windows or versions of Unix, along with their software applications. The paper describes the development of the Crusoe chips     

Programmable implementations of xDSL transceiver systems

After a background on digital subscriber line (DSL) technology, this article evaluates the trade-offs between programmable and custom implementations of communications products with an emphasis on xDSL modems. These trade-offs include time to market, risk, flexibility, power consumption, and cost. A key issue is the processing power required to implement the modem. The article takes a detailed look at the processing power required to implement an ADSL or VDSL modem on a programmable platform. It is demonstrated that today's digital signal processors meet the processing power requirements for an ADSL modem, and it is estimated that the processing requirements of a VDSL modem will be met in the near future     

Low‐Power Design of Hardware One‐Time Password Generators for Card‐Type OTPs

Since card‐type one‐time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token‐type OTPs, it is necessary to implement power‐efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low‐power small‐area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real‐world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software‐based OTP, respectively.     

Power-thermal profiling of software applications

Power consumption and heat dissipation are becoming the major factors that limit the performance evolution of current state-of-the-art microprocessors. As they become key elements in the design of both high performance computers and battery powered devices, different power and thermal management strategies have been proposed and implemented during the last years in order to overcome this performance limitation. Considering that software applications have a large impact on power consumption and thermal map of the CPU cores, these design strategies tend to be addressed at higher levels even as they are usually implemented at lower levels of systems abstraction. The work presented in this paper evaluates the relation between power consumption and thermal response of CPU cores when different software applications are executed. The goal of this study is to identify how software applications can be used in thermal management process and whether it is feasible to implement thermal-aware software applications.     

Personal Computer Communications Via Telephone Facilities

Communication from terminals to other terminals and to computing service systems has been an important aspect of data communications since the early 1960's. When personal computers arrived on the scene, in the 1970's, the use of telephone facilities and modems for communications was a natural extension of existing technology. Now, however, many modems have "intelligence" and can be controlled from their electrical interface, communication software is available to facilitate the use of a modem and coordinate the communication process, and there are many uses for personal computer communications. Some of the hardware, software, and computing services for personal computer communications are discussed in this paper.     

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Scheduling and binding are two tasks found in high-level synthesis of hardware as well as in compiling software. These tasks are realized on graphs that are models of the hardware or of the software to be compiled to run on a specific processor. Scheduling focuses on determining the start execution time of each node in the graph. Binding is the task of assigning each node in the graph to a specific computational element. Realize binding before or after scheduling can exclude generating high-quality designs (hardware or binary code). The latter statement is true in particular in the era of design for low power. Do not combine scheduling and binding can lead to designs with high switching activities and hence to high power consumption. To the best of our knowledge, there is no approach at this moment that addresses the problem of unifying scheduling and binding with an exact algorithm to produce designs with reduced power consumption. Known approaches to that problem are heuristics. That problem is NP-hard in general, since it is the composition of two NP-hard problems. Also, it has not yet been formulated in the literature. The problem becomes more complex when one has to deal with cyclic graphs and/or there are constraints to be met such as timings. For cyclic graphs, one has to integrate retiming in the unification of scheduling and binding. We propose a mathematical formulation to that problem. We extend this formulation to solve the problem of combining modulo scheduling, binding, and retiming under timings and resources constraints while reducing power consumption due to switching activities. The proposed approach is tested using known benchmarks. Based on obtained numerical results, this approach is able to reduce power consumption by 33.24% on average, with an average of 33.83 s as a run time.     

星形拓扑无线传感器网络低功耗技术研究

针对无线传感器网络在某些特定领域所需的近距离、低功耗无线通信要求,设计并实现了一款基于MSP430F149单片机和CC1100无线芯片的无线通信模块,介绍了系统架构,并从硬件和软件两个方向进行了低功耗优化设计。测试结果表明,利用该无线通信模块设计方案组建的星型网络,具有体积小,功耗低及稳定性高等特点,能满足近距离、低功耗的无线通信要求。     

Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform

Software-defined radio (SDR) is a new technology transitioning from research into commercial markets. SDR moves hardware-dominant baseband processing of multiple wireless communication protocols into software on a single chip. New cellular standards, such as HSPA+, LTE, and LTE+, require speeds in excess of 40 Mbps. SNOW 3G is a new stream cipher approved for use in these cellular protocols. Running SNOW 3G in software on our SDR platform provides a throughput of 19.1 Mbps per thread for confidentiality and 18.3 Mbps per thread for integrity. To have secure cellular communications in SDR platforms for these new protocols, the performance of security algorithms must be improved. This paper presents instruction set architecture (ISA) extensions and hardware designs for cellular confidentiality and integrity algorithms using SNOW 3G. Our ISA extensions and hardware designs are evaluated for the Sandbridge Sandblaster^? 3011 (SB3011) SDR platform. With our new SNOW 3G instructions, the performance of confidentiality and integrity improve by 70 and 2%, respectively. For confidentiality, power consumption increased by 2%, while energy decreased by 40%. For integrity, power consumption remained consistent, while energy decreased by 2%.     

基于MSP430系列单片机的CAN总线接口转换卡设计

TI公司的MSP430系列单片机是一种超低功耗的混合信号控制器,具有丰富的片内外设,有极其广阔的应用范围.介绍基于MSP430系列单片机的RS232/RS485 CAN总线通信转换接口的设计与实现,重点讨论其硬件配置和软件功能,给出电气原理和软件流程.     

Software-driven sensor networks for short-range shallow water applications

Most existing underwater networks target deep and long range oceanic environments, which has led to the design of power hungry and expensive underwater communication hardware. Because of prohibitive monetary and energy cost of currently over-engineered communication hardware, dense deployments of shallow water sensor networks remain an elusive goal. To enable dense shallow water networks, we propose a network architecture that builds on the success of terrestrial sensor motes and that relies on the coupling of software modems and widely available speakers and microphones in sensor motes to establish acoustic communication links. In this paper, we analytically and empirically explore the potential of this acoustic communication system for the underwater environment. Our experimental approach first profiles the hardware in water after waterproofing the components with elastic membranes. The medium profiling results expose the favorable frequencies of operation for the hardware, enabling us to design a software FSK modem. Subsequently, our experiments evaluate the data transfer capability of the underwater channel with 8-frequency FSK software modems. The experiments within a 17 × 8 m controlled underwater environment yield an error-free channel capacity of 24 bps, and they also demonstrate that the system supports date rates between 6 and 48 bps with adaptive fidelity.     

超低功耗温度测量显示系统的设计与应用

介绍了一种超低功耗温度测量显示系统的实现方法,给出了其硬件连接方式及软件工作流程,并具体说明了微控制器如何通过12(=总线读取数字温度传感器的温度测量值并显示的过程.在如何实现系统的超低功耗方面也作了详细的描述,最后还详细介绍了该系统的应用场合,为超低功耗温度测量显示系统的实现与应用提供了参考.     

Instruction Scheduling for Low Power

Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems.In this paper, we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. Our experimentation with these scheduling techniques shows that the best scheduling from the performance perspective is not necessarily the best scheduling from the energy perspective. Further, scheduling techniques that consider both energy and performance simultaneously are found to be desirable, that is, these techniques are quite successful in reducing energy consumption and their performance (in terms of execution cycles) is comparable to that of a pure performance-oriented scheduling. We also illuminate the inherent approximations and difficulties in building energy models for enabling energy-aware instruction scheduling and explore alternative options using cycle-accurate energy simulator. The simulation results show that the energy-oriented scheduling reduces energy consumption by up to 30% compared to the performance-oriented scheduling.     

Design and Implementation of Modular FPGA-Based PID Controllers

In this paper, modular design of embedded feedback controllers using field-programmable gate array (FPGA) technology is studied. To this end, a novel distributed-arithmetic (DA)-based proportional-integral-derivative (PID) controller algorithm is proposed and integrated into a digital feedback control system. The DA-based PID controller demonstrates 80% savings in hardware utilization and 40% savings in power consumption compared to the multiplier-based scheme. It also offers good closed-loop performance while using less resources, resulting in cost reduction, high speed, and low power consumption, which is desirable in embedded control applications. The complete digital control system is built using commercial FPGAs to demonstrate the efficiency. The design uses a modular approach, so that some modules can be reused in other applications. These reusable modules can be ported into Matlab/Simulink as Simulink blocks for hardware/software cosimulation or integrated into a larger design in the Matlab/Simulink environment to allow for rapid prototyping applications.     

Deferrable load scheduling under imperfect data communication channel

In smart grid, the real‐time pricing is implemented to motivate power consumers to change their consumption profile dynamically. With the real‐time pricing, a deferrable load can be scheduled by its scheduler optimally so that the power consumption cost will be minimized. However, when the data communication in smart grid suffers from interference, congestion, malfunction in devices, or even cyber attack, it is possible that the power price information cannot be transmitted successfully to the scheduler. As a result, the scheduling performance will be negatively affected by the suboptimal decision‐making because of incomplete power price information. To overcome this problem, a partially observable Markov decision process based deferrable load scheduling algorithm is proposed. Besides, the implementation of a standby alternative channel with the purpose to improve the reliability of the data communication in smart grid is also discussed in this paper. The numerical results show that the proposed partially observable Markov decision process based algorithm and the implementation of standby channel can effectively improve the scheduling performance when the scheduler lacks actual price information. Copyright © 2014 John Wiley & Sons, Ltd.     

嵌入式系统抗缓冲区溢出攻击的硬件防御机制研究

嵌入式系统设计时由于成本和功耗等方面的考虑而较少重视安全性,而一般采用的软件防御方式无法满足嵌入式系统在实时性和可靠性上的要求,缓冲区溢出作为最常见的软件安全漏洞对嵌入式系统安全构成严重威胁.文中构建了一种基于细粒度指令流监控(FIFM)的硬件防御机制,通过虚拟执行单元虚拟执行程序,在攻击发生之前检测攻击行为.实验结果表明FIFM能很好的防御典型的缓冲区溢出攻击,而且FIFM不需要修改程序,不破坏流水线完整性,对系统的性能影响小,本文的防护机制可以应用于其他嵌入式系统设计中以动态防御缓冲区溢出攻击.     

SDR receiver computational model for application in power control

Software-defined radio (SDR) permits dynamic switches of the employed radio access technology (RAT), over-the-air (OTA) software updates, software and hardware reuse. This extended flexibility comes at the price of a higher computing complexity and, in particular, the energy consumption at the receiver. The analysis of the computational profile of signal processing algorithms is of great importance in SDR for understanding the implication on the energy consumption. Several signal processing algorithms show a different profile as a function of the signal quality perceived at the receiver antenna. Therefore, power control policies have an implication on the computational performance of SDR receivers. Understanding the behaviour of these algorithms allows trading transmitted power against receiver energy consumption. This paper presents a model for characterizing the computational profile of Turbo and LDPC decoders and demonstrates is applicability in existing power control strategies.