A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

Evidence of crossover phenomena in wind-speed data

In this paper, a systematic analysis of hourly wind-speed data obtained from three potential wind-generation sites (in North Dakota) is analyzed. The power spectra of the data exhibited a power-law decay characteristic of 1/f/sup /spl alpha// processes with possible long-range correlations. Conventional analysis using Hurst exponent estimators proved to be inconclusive. Subsequent analysis using detrended fluctuation analysis revealed a crossover in the scaling exponent (/spl alpha/). At short time scales, a scaling exponent of /spl alpha//spl sim/1.4 indicated that the data resembled Brownian noise, whereas for larger time scales the data exhibited long-range correlations (/spl alpha//spl sim/0.7). The scaling exponents obtained were similar across the three locations. Our findings suggest the possibility of multiple scaling exponents characteristic of multifractal signals.     

Reverse high-speed packet data physical layer enhancements in cdma2000 1/spl times/EV-DV

The rapid growth of Internet-based applications calls for design of a high-speed wireless packet data communication system. This anticipated increase in future mobile wireless packet data services has challenged the current 3G standardization bodies to respond with evolved 3G system specifications capable of providing increased data throughput. In response to such a need, 3GPP2 recently completed the enhanced reverse link standardization effort of the CDMA technology flagship, cdma2000/spl reg/ by completing the definition of the 1/spl times/EV-DV 1/spl times/ system. 1/spl times/EV-DV achieves higher data throughput while simultaneously providing coexisting and backward-compatible voice services within the same spectrum. This feature of 1/spl times/EV-DV allows wireless operators to manage the voice and data loading in their system more efficiently. This article describes the physical layer reverse link enhancements in cdma2000 revision D that are necessary to support 1/spl times/EV-DV.     

A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability

A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million instructions per second and up to six concurrent operations in each instruction. Two DSPs, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16/spl times/16/spl rarr/40-bit multiplier accumulator and 16-bit ALU, both with multiprecision support in hardware. Also implemented are two static data RAMs (128/spl times/16 or 256/spl times/16), a data ROM (51/spl times/16), a 15-word three-port register file, three address computation units, and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32/spl times/40; ROM: 987/spl times/40) or off-chip program memory (up to 64K/spl times/40). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.     

On incremental sigma-delta modulation with optimal filtering

The paper presents a quantization-theoretic framework for studying incremental sigma-delta (/spl Sigma//spl Delta/) data conversion systems. The framework makes it possible to efficiently compute the quantization intervals and hence the transfer function of the quantizer, and to determine the mean square error (MSE) and maximum error for the optimal and conventional linear filters for first and second order incremental /spl Sigma//spl Delta/ modulators. The results show that the optimal filter can significantly outperform conventional linear filters in terms of both MSE and maximum error. The performance of conventional /spl Sigma//spl Delta/ data converters is then compared to that of incremental /spl Sigma//spl Delta/ with optimal filtering for bandlimited signals. It is shown that incremental /spl Sigma//spl Delta/ can outperform the conventional approach in terms of signal-to-noise-and-distortion ratio. The framework is also used to provide a simpler and more intuitive derivation of the Zoomer algorithm.     

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

Incidence angle dependence of the statistical properties of C-band HH-polarization backscattering signatures of the Baltic Sea ice

Incidence angle dependence of three statistical parameters-the mean of the backscattering coefficient (/spl sigma//spl deg/), standard deviation, and autocorrelation coefficient of texture (/spl sigma//sub T/ and /spl rho//sub T/)-of the C-band horizontal-horizontal (HH) polarization backscattering signatures of the Baltic Sea ice are investigated using RADARSAT ScanSAR Narrow images and helicopter-borne Helsinki University of Technology Scatterometer (HUTSCAT) data. The analysis of the large amount of data shows that the relationship between the mean /spl sigma//spl deg/ in decibel scale and the incidence angle in the range from 19/spl deg/ to 46/spl deg/ is usually well described by a linear model. In general, the RADARSAT and HUTSCAT results agree with each other, and they are also supported by theoretical backscattering model calculations; the more deformed the ice, the smaller the slope between /spl sigma//spl deg/ and the incidence angle, and the higher the moisture content of snow or ice, the larger the slope. The derived /spl sigma//spl deg/ incidence angle dependencies can be used to roughly compensate the /spl sigma//spl deg/ incidence angle variation in the SAR images to help their visual and automated classification. The variability of /spl sigma//sub T/ and /spl rho//sub T/ with the increasing incidence angle is insignificant compared to the variability within each ice type. Their average changes with the incidence angle are so small that, in practice, their trends do not need to be compensated. The results of this study can be utilized when developing classification algorithms for the RADARSAT ScanSAR and ENVISAT HH-polarization Wide Swath images of the Baltic Sea ice.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

Implant-free high-mobility flatband MOSFET: principles of operation

Principles of operation of implant-free enhancement-mode MOSFETs (flatband MOSFET) are discussed. Epitaxial-layer structures designed for use in implant-free enhancement-mode devices and employing a high-/spl kappa/ dielectric (/spl kappa//spl cong/20) and a strained InGaAs channel layer with a thickness of 10 nm have been manufactured on GaAs substrate. Proceeding from measured electron mobility /spl mu/ as a function of the sheet-carrier concentration, enhancement-mode design considerations, saturation current I/sub Dss/, and mobility requirements are discussed using two-dimensional device simulations. For the flatband MOSFET to compete successfully with other device designs, certain minimum channel mobilities are required. For RF applications, /spl mu/ should exceed 5000 cm/sup 2//Vs while high-performance MOSFETs for digital applications may require even higher mobility for optimum operation. Finally, measured data of first 1-/spl mu/m-GaAs-flatband enhancement-mode MOSFETs are presented; the saturation velocity of the InGaAs channel layer is derived; and measured I/sub Dss/ data are compared to the results obtained by simulations.     

Fiber-Optical Transmission Between 0.8 and 1.4 /spl mu/m

The present state of the art and expected development in discrete components for Fiber-optic transmission systems are reviewed. Predicted performance of fiber systems in the 0.85, 1.06, and 1.27 /spl mu/m regions is presented, and the advantages of longer wavelength operation quantified. Itisconcluded that operation near 1.27 /spl mu/m is particularly attractive for a) moderate data rate systems employing LED's and multimode fibers whose chromatic dispersion and attenuation are greatly reduced compared with 0.85 and 1.06 /spl mu/m, and b) high data rate systems employing lasers and monomode fibers. In systems employing lasers and graded index multimode fibers, the advantage of 1.27/spl mu/m versus 1.06 /spl mu/m operation is not as pronounced, although transmission distances at both of these longer wavelengths are significantly increased from those at 0.85 /spl mu/m.     

The Microwave Reflective Properties of Water Surfaces-I: The Reflectivity of Smooth Water at 19.24 and 22.43 GHz as Measured with a Free-Wave Microwave Reflectometer

The reflectivity of smooth water has been measured with a free-wave reflectometer at frequencies of 19.24 and 22.43 GHz and for temperatures between 0/spl deg/ and 40/spl deg/C. Reproducibility of the data for water temperatures below 20/spl deg/C is better than /spl plusmn/ 0.15 percent and the absolute accuracy of the reflectometer is thought to be /spl plusmn/ 0.5 percent. The results deviate significantly from the early reflectivity measurements of Saxton and Lane but agree to within experimental error with values calculated from the absorption cell measurements of Lane and Saxton.     

Electron beam direct-write tunable polymeric waveguide grating filter

We report a tunable electron beam direct-write polymeric waveguide Bragg grating filter based on a negative tone epoxy, The waveguide filter, with a 5-mm-long first-order grating, exhibits a transmission peak of -27 dB and a 3-dB bandwidth of /spl sim/0.8 nm, and there is an excellent agreement between experimental data and simulation results. The temperature response of the filter is also characterized. The rate of change of refractive index dn/dT is /spl sim/ -1.8 /spl times/ 10/sup -4///spl deg/1C at 1550-nm wavelength for both transverse electric and transverse magnetic polarizations, and the rate of change of peak wavelength d/spl lambda//dT is /spl sim/ -0.14 nm//spl deg/C. The tuning performance is comparable to other grating devices fabricated using multiple processing steps.     

Decoding by linear programming

This paper considers a natural error correcting problem with real valued input/output. We wish to recover an input vector f/spl isin/R/sup n/ from corrupted measurements y=Af+e. Here, A is an m by n (coding) matrix and e is an arbitrary and unknown vector of errors. Is it possible to recover f exactly from the data y? We prove that under suitable conditions on the coding matrix A, the input f is the unique solution to the /spl lscr//sub 1/-minimization problem (/spl par/x/spl par//sub /spl lscr/1/:=/spl Sigma//sub i/|x/sub i/|) min(g/spl isin/R/sup n/) /spl par/y - Ag/spl par//sub /spl lscr/1/ provided that the support of the vector of errors is not too large, /spl par/e/spl par//sub /spl lscr/0/:=|{i:e/sub i/ /spl ne/ 0}|/spl les//spl rho//spl middot/m for some /spl rho/>0. In short, f can be recovered exactly by solving a simple convex optimization problem (which one can recast as a linear program). In addition, numerical experiments suggest that this recovery procedure works unreasonably well; f is recovered exactly even in situations where a significant fraction of the output is corrupted. This work is related to the problem of finding sparse solutions to vastly underdetermined systems of linear equations. There are also significant connections with the problem of recovering signals from highly incomplete measurements. In fact, the results introduced in this paper improve on our earlier work. Finally, underlying the success of /spl lscr//sub 1/ is a crucial property we call the uniform uncertainty principle that we shall describe in detail.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

A Digital Latching Ferrite Strip Transmission Line Phase Shifter

This paper is concerned with the development of a new type of latching phase shifter which combines submicrosecond switching with a compact strip transmission line structure. Digital increments of nonreciprocal phase shift are obtained by "latching" or switching the magnetization of appropriate square loop garnet or ferrite materials from one remanent state to another. The following data have been obtained for a four-bit, C-band model utilizing yttrium iron garnet (4/spl pi/M/sub 8/ = 1600 G): Center Frequency---5.45 Gc/s Phase Deviation---/spl les//spl plusmn/3 percent over an 8 percent frequency band Insertion Loss--- <0.9 db VSWR--- <1.50 Switching Time--- <0.3/spl mu/s with a 130 V, 13 amp pulse Switching Energy--- <200 /spl mu/J for 180/spl deg/ bit Length--- <6 inches.     

Symbol-intersecting codes

We consider codes consisting of arrays over an alphabet F, in which certain intersecting subsets of n/spl times/m coordinates are required to form codewords of length n in prescribed codes over the alphabet F/sup m/. Two specific cases are studied. In the first case, referred to as a singly-intersecting coding scheme, the user data is mapped into n/spl times/(2m-1) arrays over an alphabet F, such that the n/spl times/m subarray that consists of the left (respectively, right) m columns forms a codeword of a prescribed code of length n over F/sup m/; in particular, the center column is shared by the left and right subarrays. Bounds are obtained on the achievable redundancy region of singly-intersecting coding schemes, and constructions are presented that approach-and sometimes meet-these bounds. It is shown that singly-intersecting coding schemes can be applied in a certain model of broadcast channels to guarantee reliable communication. The second setting, referred to as a fully-intersecting coding scheme, maps the user data into n/spl times/m/spl times/m three-dimensional arrays in which parallel n/spl times/m subarrays are all codewords of the same prescribed code over F/sup m/. Bounds and constructions are presented for these codes, with the analysis based on representing the n/spl times/m/spl times/m arrays as vectors over certain algebras on m/spl times/m matrices.     

A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications

A 6.5-GHz FSK modulator suitable for low power wireless sensor network is presented. The energy efficient modulator employs closed-loop direct VCO modulation to achieve high data rate, multistage variable loop bandwidth technique for fast startup time and /spl Sigma/-/spl Delta/ for reduced power consumption in the synthesizer with fine resolution in frequency channel selection. The modulator, implemented using 0.25-/spl mu/m CMOS, achieves 20-/spl mu/s startup time with an effective data rate of 2.5 Mb/s while consuming 22 mW.     

An in-place architecture for the deblocking filter in H.264/AVC

This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 /spl times/ 4 blocks instead of whole 16 /spl times/ 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K /spl times/ 1K@30 Hz video application when clocked at 73.73 MHz by using 0.25-/spl mu/m CMOS technology.     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.