The design and implementation of a grammar-based data generator

DGL is a context-free grammar-based language for generating test data. Although many of the features of DGL are implemented in a straighforward way, the implementation of several of the most important features is neither trivial nor obvious. Before one can understand the implementation of these features, however, it is necessary to understand the overall structure of the compiler and its output, which was designed to be flexible enough to incorporate new features easily. Variables and chains are two of the most important features of DGL, and also two of the trickiest features to implement. The run-time dictionaires, which are built into the C code generated by the compiler, are implemented as pure code rather than as table-look-up routines. The compiler itself is reasonably straightforward, except for the expansion of character sets and compile-time macros. These two features can cause the ‘multi-dimensional’ expansion of a string, the implementation of which must be carefully designed.     

分支语句重构算法的研究与应用

由于条件分支语句的多重嵌套,导致代码的逻辑结构不清晰,可读性差,降低了生成基本路径集时划分基本块的效率。据此,提出一种代码自动化重构方法,该方法运用编译原理中语法分析的自下而上分析方法和归约思想,能够对嵌套的if-else条件语句实现自动化调整,实现代码结构的清晰化,更适用于生成基本路径集的工具,该方法提高了生成基本路径集的效率。而对于基于模型代数的基本路径集生成工具,改进了生成模型代数表达式的算法,并且能够准确地生成基本路径集。最后通过实验对案例进行对比,验证了重构方法及改进算法的有效性。     

A transportable extendable compiler

This report describes the development of a transportable extendable self-compiler for the language SIMPL-T. SIMPL-T is designed as the base language for a family of languages. The structure of the SIMPL-T compiler and its transportable bootstrap are described. In addition, the procedures for generating a compiler for a new machine and for boot-strapping the new compiler on to the new machine are demonstrated.     

基于GCC的VLIW编译系统研究

VLIW机器在单个机器周期中同时发射并执行多个的并行操作,从而获得较高的指令级并行度,这些操作之间的依赖分析和调度工作则被完全交给相应的编译器执行,因此VLIW的并行性能能否充分发挥取决于VLIW体系结构相关编译器的质量。GNU开发的GCC是被最广泛使用的编译系统之一,它具有多语言、多平台支持的能力和开放的结构,能够运用各种成熟的常规编译优化技术生成高效的代码。文章分析了VLIW及GCC的结构特点,提出了一种基于GCC的VLIW编译系统设计方案,利用GCC进行RTL中间代码一级的体系结构无关优化和少量体系结构相关优化,在汇编代码一级针对VLIW结构进行体系结构相关的优化,从而充分利用GCC的成熟编译技术快速开发高效的VLIW多语言编译系统。     

Automatic data structure selection and transformation for sparsematrix computations

The problem of compiler optimization of sparse codes is well known and no satisfactory solutions have been found yet. One of the major obstacles is formed by the fact that sparse programs explicitly deal with particular data structures selected for storing sparse matrices. This explicit data structure handling obscures the functionality of a code to such a degree that optimization of the code is prohibited, for instance, by the introduction of indirect addressing. The method presented in this paper delays data structure selection until the compile phase, thereby allowing the compiler to combine code optimization with explicit data structure selection. This method enables the compiler to generate efficient code for sparse computations. Moreover, the task of the programmer is greatly reduced in complexity     

Ada95编译系统中多平台技术的研究

支持多语种、多平台是当前编译技术的发展趋势,它适应了当前计算机系统迅猛更新的需要。文中提出了一个适用于不同计算机平台的多平台Ada95编译系统的模型,在此基础上讨论了Ada95编译系统中多平台支持的三个关键技术:平台配置机制、运行库多平台支持技术和多平台代码生成支持策略,并描述了相应的设计与实现方法。     

OPTIMA—A portable PCODE optimizer

This paper describes the design and implementation of OPTIMA, a Portable optimizer for the PASCAL-P4 compiler. The PASCAL-P4 compiler generates code, called PCODE, for a hypothetical stack computer. The stack computer is easy to simulate or to emulate on a wide range of computer architectures. However, the code produced for it by PASCAL-P4 is unoptimized and inefficient when emulated on conventional computers. OPTIMA improves the code which is produced by the compiler. It has three levels of optimization: PCODE transformations, TUPLE transformations and Code generation. Programs processed by the optimizer are substantially smaller and faster than before optimization. OPTIMA was implemented for the Weizmann Institute of Science GOLEM-B computer.     

New Shape Analysis and Interprocedural Techniques for Automatic Parallelization of C Codes

Automatic parallelization of codes with complex data structures is becoming very important. These complex, and often recursive, data structures are widely used in scientific computing. Shape analysis is one of the key steps in the automatic parallelization of such codes. In this paper we extend the Static Shape Graph (SSG) method to enable the successful and accurate detection of complex doubly-linked structures. We have also included an interprocedural analysis in our framework. These techniques have been implemented in a compiler, which has been validated for several C codes. In particular, we present the results the compiler achieves for the C sparse LU factorization algorithm and for a recursive code generating a tree data structure. The output SSG perfectly describes the complex data structure used in these codes.     

Evaluating compiler technology for control-flow optimizations for multimedia extension architectures

This paper addresses how to automatically generate code for multimedia extension architectures in the presence of conditionals. We evaluate the costs and benefits of exploiting branches on the aggregate condition codes associated with the fields of a superword (an aggregate object larger than a machine word) such as the branch-on-any instruction of the AltiVec. Branch-on-superword-condition-codes (BOSCC) instructions allow fast detection of aggregate conditions, an optimization opportunity often found in multimedia applications. This paper presents compiler analyses and techniques for generating efficient parallel code using BOSCC instructions. We evaluate our approach, which has been implemented in the SUIF compiler, through a set of experiments with multimedia benchmarks, and compare it with the default approach previously implemented in our compiler. Our experimental results show that using BOSCC instructions can result in better performance for applications where the aggregate condition codes of a superword often evaluate to the same value.     

Towards a verified compiler prototype for the synchronous language SIGNAL

SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nuclear power plants. This paper reports a compiler prototype for SIGNAL. Compared with the existing SIGNAL compiler, we propose a new intermediate representation (named S-CGA, a variant of clocked guarded actions), to integrate more synchronous programs into our compiler prototype in the future. The front-end of the compiler, i.e., the translation from SIGNAL to S-CGA, is presented. As well, the proof of semantics preservation is mechanized in the theorem prover Coq. Moreover, we present the back-end of the compiler, including sequential code generation and multithreaded code generation with time-predictable properties. With the rising importance of multi-core processors in safetycritical embedded systems or cyber-physical systems (CPS), there is a growing need for model-driven generation of multithreaded code and thus mapping on multi-core. We propose a time-predictable multi-core architecture model in architecture analysis and design language (AADL), and map the multi-threaded code to this model.     

支持并行模拟的Verilog编译技术研究与实现

并行HDL模拟是加速大型复杂的VLSI系统模拟验证的有效方法，支持并行模拟的HDL编译技术是其中的关键技术，文章提出了一种支持并行模拟的Verilog编译技术，编译器将Verilog描述转换成C＋＋代码，最后与并行模拟核心库编译链接生成可执行并行程序。文章将编译器构成，代码生成方法和并行模拟核心库，该技术已经在并行Verilog模拟器ParaVer上实现。     

反投机技术研究

投机优化技术作为一种先进的现代编译技术,有效地提高了指令执行的并行性。然而,在逆向工程中,有时要实现代码的跨平台移植,而投机优化技术又受硬件平台的制约;有时需要优化代码的结构,使程序的逻辑结构易于理解;这些都要求消除这种与硬件息息相关的优化技术。论文基于IA-64平台,提出了一种反投机处理算法,对ICC编译器编译后的可执行二进制代码进行处理,消除代码中的投机优化,将其转换成等价的没有投机优化的指令序列,这样使反投机后的代码更容易理解,而且在逆向工程中摆脱了硬件的限制。测试表明该反投机技术可以对ICC编译后的代码进行有效处理。     

对用户交互响应进行加速的即时编译技术

对于影响用户交互响应速度的瓶颈代码段,现有即时编译器存在无法准确选取和在程序启动阶段没有可用的本地码进行加速的问题,这影响了即时编译技术在用户交互响应方面的加速效果。为此,对即时编译器原有的代码选择策略和编译模式进行了改进。在代码选择策略方面,应用程序可以根据实际运行情况主动选择要编译的代码段,保证所有影响用户交互响应速度的瓶颈代码段都能被选取并被加速;在编译模式方面,本次编译得到的本地码可以保存并供程序下次运行时使用,保证在程序启动阶段也有本地码可用来加速。应用程序启动速度的实验表明,改进的即时编译器能够提升1倍的用户响应速度。     

Compiler transformations for effectively exploiting a zero overhead loop buffer

A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequence of instructions that will be executed a specified number of times without incurring any loop overhead. Unlike loop unrolling, a loop buffer can be used to minimize loop overhead without the penalty of increasing code size. In addition, a ZOLB requires relatively little space and power, which are both important considerations for most DSP applications. This paper describes strategies for generating code to effectively use a ZOLB. We have found that many common code improving transformations used by optimizing compilers on conventional architectures can be easily used to (1) allow more loops to be placed in a ZOLB, (2) further reduce loop overhead of the loops placed in a ZOLB, and (3) avoid redundant loading of ZOLB loops. The results given in this paper demonstrate that this architectural feature can often be exploited with substantial improvements in execution time and slight reductions in code size for various signal processing applications. Copyright © 2004 John Wiley & Sons, Ltd.     

An optimizing compiler for the icon programming language

Compiling code for the Icon programming language presents several challenges, particularly in dealing with types and goal-directed expression evaluation. In order to produce optimized code, it is necessary for the compiler to know much more about operations than is necessary for the compilation of most programming languages. This paper describes the organization of the Icon compiler and the way it acquires and maintains information about operations. The Icon compiler generates C code, which makes it portable to a wide variety of platforms and also allows the use of existing C compilers for performing routine optimizations on the final code. A specially designed implementation language, which is a superset of C, is used for writing Icon's run-time system. This language allows the inclusion of information about the abstract semantics of Icon operations and their type-checking and conversion requirements. A translator converts code written in the run-time language to C code to provide an object library for linking with the code produced by the Icon compiler. The translation process also automatically produces a database that contains the information the Icon compiler needs to generate and optimize code. This approach allows easy extension of Icon's computational repertoire, alternate computational extensions, and cross compilation.     

一种改进数据流图的子字并行程序表示方法

论文致力于对图像处理算法的串行C程序进行子字并行分析,并重定向到带有多媒体扩展的通用处理器和多媒体专用嵌入式微处理器。图像处理算法的特点决定其是内在可并行的,这种并行粒度介于数据并行(DLP)和指令级并行(ILP)之间,称之为子字并行。但是,当前的编译技术很难充分挖掘和定位程序基本块内的子字并行,对此设计了一种基于流图程序表示的编译方法,能够从串行程序中显式地定位子字并行。扩展了编译器的功能,增加了特定的模式库,基于模式识别的控制流和数据流分析后,产生特定的子字并行流图(SWFG,Sub-WordFlowGraph),并将该图作为中间表示,提供给子字并行指令选择,进而实现有效的子字并行代码产生。     

Using profile information to assist classic code optimizations

This paper describes the design and implementation of an optimizing compiler that automatically generates profile information to assist classic code optimizations. This compiler contains two new components, an execution profiler and a profile-based code optimizer, which are not commonly found in traditional optimizing compilers. The execution profiler inserts probes into the input program, executes the input program for several inputs, accumulates profile information and supplies this information to the optimizer. The profile-based code optimizer uses the profile information to expose new optimization opportunities that are not visible to traditional global optimization methods. Experimental results show that the profile-based code optimizer significantly improves the performance of production C programs that have already been optimized by a high-quality global code optimizer.     

Attributed linear intermediate representations for retargetable code generators

This paper illustrates the usefulness of an attributed prefix linear intermediate representation for compiler code generation. In separating the machine-independent and machine-dependent aspects of a compiler, we discuss the advantages and disadvantages of an attributed linear intermediate representation with respect to tree-structured intermediate representations. Some of these issues are relevant to fundamental questions of compiler structure with particular emphasis on retargetability. We discuss our implementation experience using this linear intermediate representation with a table-driven code generation scheme for a variety of target architectures.     

A LIS compiler for GCOS-7

This paper describes the implementation of a LIS compiler for GCOS-7. LIS is a high level system implementation language developed at CII-Honeywell Bull during the middle 1970s, and experience with the language and its implementation have largely influenced the design of Ada. The design of the compiler was particularly aimed at efficient code generation. Design decisions concerning the run-time organization in relation to procedure call and separate compilation are discussed. The structure of the compiler is described. The articulation between the different phases of the code generator is emphasized. Experience with the bootstrap is related.