Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs

Using a novel HfLaO gate dielectric for nMOSFETs with different La composition, we report for the first time that TaN (or HfN) effective metal gate work function can be tuned from Si mid-gap to the conduction band to fit the requirement of nMOSFETs. This is explained by the change of interface states and Fermi pinning level by adding La into HfO/sub 2/. The superior performances of the nMOSFETs compared with those using pure HfO/sub 2/ gate dielectric are also reported, in terms of higher crystallization temperature and higher drive current I/sub d/ without sacrifice of very low gate leakage current, i.e. 5-6 orders reduction compared with SiO/sub 2/ at the same equivalent oxide thickness of /spl sim/1.2-1.8 nm.     

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.     

First principles study of Nb-W bilayer metal gate electrode

First principles calculations are performed to study the electronic structure and related properties of the Nb-W interface within NbW multilayer metal gate electrode. It is found that the surface work functions of NbW multilayers are located between those of pure Nb and W surfaces due to the strain effect from the lattice dismatch. The interface energy of Nb(1 1 0)/W(1 1 0) is calculated to be −0.17 J/m², implying that the Nb-W interface is energetically favorable. Additionally, it is found that the interface dipoles are formed in the interface region to balance the work function difference of W and Nb, and the dipole layers are mainly due to the contributions of interface atoms with a very small contribution from the second atomic layers from the interface. It is of interest to note that the interface W atoms give out a little bit more electrons than the interface Nb atoms during the formation of the interface dipole and that these changes are closely related to the DOS changes.     

Impacts of gate structure on dynamic threshold SOI nMOSFETs

The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

Highly efficient green top-emitting organic light-emitting devices with metal electrode structure

In this work, the electrical and optical characteristics of top-emitting organic light-emitting device (TEOLED) using metal Ag as anode with different thicknesses have been investigated. The emission peak of fabricated TEOLED is 512 nm for a full-width at half-maximum (FWHM) of 48 nm in forward direction. The TEOLED turns on at 3 V with luminance of 2.38 cd/m² and reaches 16,300 cd/m² at 9 V. The maximum of current efficiency is 5.2 cd/A at 7 V, corresponding to the external quantum efficiency of 1.72%.     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Yb-doped Ni FUSI for the n-MOSFETs gate electrode application

In this letter, an n-type near-band edge fully silicided (FUSI) material-Yb-doped Ni FUSI is demonstrated for the first time. By doping Yb into Ni FUSI, it is shown that while maintaining the same equivalent oxide thickness and the similar device reliability, the work function of Ni FUSI (on SiON dielectrics) could be tuned from 4.72 to 4.22 eV. Yb-doped Ni FUSI is promising for the gate electrode application in n-MOSFETs.     

A nitride-isolated molybdenum-polysilicon gate electrode for MOS VLSI circuits

A new gate electrode structure is demonstrated. The low-resistive gate electrode consists of a triple layer of molybdenum and polysilicon films isolated with an ultrathin silicon-nitride film, namely MTP-metal/tunneling nitride/polysilicon. The tunneling nitride, which is grown by direct thermal nitridation of silicon, avoids silicidation of molybdenum and diffusion of impurities resulting in a thin SiO2film of good quality. Characteristics of discrete FET's can be designed like those of conventional silicon-gate devices. No instability due to the tun, neling nitride has been observed in both dc and high-speed switching operations. The technique is useful for MOS VLSI circuits.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Highly reliable and low-power magnetic full-adder designs for nanoscale technologies

The MTJ-based circuits have been considered as a candidate for next generation digital integrated circuits thanks to their attractive features such as nonvolatility, low leakage current, high endurance, and CMOS integration compatibility. However, incurred energy and delay by reconfiguration of their employed conventional MTJs limit their application. Besides, the issue of read-disturbance is another challenge in such MTJ-based circuit designs. In this article, a new magnetic-based full-adder (MFA) circuit based on a new three-terminal two-in-one magnetic tunnel junction (TIO-MTJ) cell is proposed. Comparing with the previous MFA circuits, the proposed circuit offers a lower energy for the write operation and also a disturbance-free reading. Two improved structures based on the proposed MFA are also suggested to obtain the advantages of nonvolatility for the power-gating architectures and also radiation hardening for the radiation harsh environments.     

高可靠性高精度的重复频率激光器电源

本文提出一种新的重复频率电源的电路,其特点是可靠性高,即使产生连续导通,脉冲灯、可控硅、整流二极管等元件也不会损坏;输出电压的重复精度高,一般可达10~(-3);线路简单,调整、操作、维修均很方便;频率稳定。