利用改善的体连接技术制备SOI LDMOSFET

对功率器件中常用的体连接技术进行了改进,利用一次硼离子注入技术形成体连接.采用与常规1μm SOI(硅-绝缘体)CMOS工艺兼容的工艺流程,在SIMOX SOI片上制备了LDMOS结构的功率器件.器件的输出特性曲线在饱和区平滑,未呈现翘曲现象,说明形成的体连接有效地抑制了部分耗尽器件的浮体效应.当漂移区长度为2μm时,开态击穿电压达到10V,最大跨导17.5mS/mm.当漏偏压为5V时,SOI器件的泄漏电流数量级为1nA,而相应体硅结构器件的泄漏电流为1000nA.电学性能表明,这种改善的体连接技术能制备出高性能的SOI功率器件.     

晶体管、MOS器件

9907350应用 Volterra 级数分析 AIGaAs/GaAs HBT 的三阶互调失真[刊]/廖小平//固体电子学研究与进展.—1998,18(4).—425～430(D)9907351薄膜 SOI 材料 MOSFET 的高温泄漏电流[刊】/冯耀兰//固体电子学研究与进展.—1998,18(4).—415～419(D)     

28 nm超薄体FD-SOI高温特性研究

研究了低阈值电压(LVT)结构的28 nm超薄体全耗尽绝缘体上硅(FD-SOI)MOSFET的高温下特性.在300℃下对器件进行测试,将FD-SOI与部分耗尽(PD)SOI进行参数对比.结合理论分析,证明了高温下超薄体FD-SOI具有比PD-SOI更低的阈值电压漂移率和亚阈值摆幅.在300℃高温下工作时,SOI MOS...     

体硅、SOI和SiCMOS器件高温特性的研究

首先介绍了体硅 MOS器件在 2 5～ 30 0℃范围高温特性的实测结果和分析 ,进而给出了薄膜 SOI MOS器件在上述温度范围的高温特性模拟结果和分析 ,最后介绍了国际有关报道的Si C MOS器件在 2 2～ 4 50℃范围的高温特性。在上述研究的基础上 ,提出了体硅、SOI和 Si C MOS器件各自所适用的温度范围和应用前景     

pn结泄漏电流对高温集成MOSFET交流性能的影响

分析了漏源pn结泄漏电流对高温MOS模拟集成电路中、工作在零温度系数(ZTC点)的MOSFET交流参数的影响。研究结果表明,pn结扩散电流对高温MOSFET的交流性能有极大的影响,而产生电流的影响则可以忽略不计。减小泄漏电流对高温MOSFET交流性能影响的重要方法是增加衬底掺杂浓度。还给出了漏源pn结泄漏电流和工作在ZTC点的漏源电流最大允许比例的计算公式。     

SOI和体硅集成电路工艺平台互补问题的探讨

本文讨论的SOI(Silicon On Insulator)是BESOI (Bonding and Etch back SOI),由于在SOI材料上制造的集成电路(IC)和常规的体硅IC相比在性能上有许多优点,因此很有发展前途.目前SOI材料的性能和体硅相比确有一些差距,其主要原因是SOI的缺陷密度需进一步降低;但是有些质量问题要进行具体分析;例如工艺中不受控的重金属杂质集中在SOI区内无法泄漏;空气中硼(B)杂质污染硅片引起电阻率的变化;衬底的硅片是直拉单晶,其高浓度氧(0)杂质在高温时外扩散到SOI中引起SOI中O浓度提高等;这些问题的起因主要是由于各种杂质在硅中和二氧化硅中扩散系数不同所引起的,这些问题的解决有的需要二个工艺平台的互补,即需要相互配合使SOI IC的质量不断提高;本文将这些杂质产生的原因,影响和改进方法作初步探讨.     

宽温区MOSFET反型层载流子迁移率的模型和测定方法

首先介绍了宽温区 (2 7～ 30 0°C) MOSFET的阈值电压、泄漏电流和漏源电流的特点以及载流子迁移率的高温模型 ;进而给出了室温下 MOSFET反型层载流子迁移率的测定方法 ,最后提出了利用线性区 I- V特性方程测定宽温区 MOSFET反型层载流子迁移率的方法 ,并给出了测试结果     

SOI前途如何

尽管SOI（绝缘体上硅）材料已经有几十年的历史了，但其应用一直被限制在抗辐射等特珠领域。然而，已有迹象表明采用8OI技术将成为当今IC主流技术。其理由是：泄漏和短为效应使得传统的体硅已不再适应先进的CMOS电路生产，而由SOI材料的隐理绝缘层呈现的隔离效应可满足先进CMOS电路的要求。最近几年来，人们已经研究开发了许多不同的SOI技术，但目前使用在集成电路生产上的只有两种：SIMOX（注入氧隔离）技术和粘合硅片技术。在SIMOX工艺中，标准硅片进行氧离于注入，然后再进行高温退火．结果在硅表层下氧和硅结合形成一层硅…     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。     

超高速CMOS/SOI51级环振电路的研制

利用CMOS/SOI工艺在4英寸SIMOX材料上成功制备出沟道长度为1μm、器件性能良好的CMOS/SOI部分耗尽器件和电路,从单管的开关电流比看,电路可以实现较高速度性能的同时又可以有效抑制泄漏电流.所研制的51级CMOS/SOI环振电路表现出优越的高速度性能,5V电源电压下单门延迟时间达到92ps,同时可工作的电源电压范围较宽,说明CMOS/SOI技术在器件尺寸降低后将表现出比体硅更具吸引力的应用前景.     

Low-power and high-stability SRAM technology using alaser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10⁴, and the source-drain leakage current is decreased by a factor of 10-10² compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs     

A temperature-dependent SOI MOSFET model for high-temperatureapplication (27 °C-300 °C)

A temperature-dependent model for long-channel silicon-on-insulator (SOI) MOSFETs for use in the temperature range 27 °C-300 °C, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the temperature-dependent effects in SOI MOSFETs (such as threshold-voltage reduction, increase of leakage current, decrease of generation due to impact ionization, and channel mobility degradation with increase of temperature) which are influenced by the uniqueness of SOI device structure, i.e. the back gate and the floating film body. The model is verified by the good agreement of the simulations with the experimental data. The model is implemented in SPICE2 to be used for circuit and device CAD. Simple SOI CMOS circuits are successfully simulated at different temperatures     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.     

Numerical study of self-heating effects of MOSFETs fabricated on SOAN substrate

A two-dimensional numerical analysis is performed to investigate the self-heating effects of metal-oxide-silicon field-effect transistors (MOSFETs) fabricated in silicon-on-aluminum nitride (SOAN) substrate. The electrical characteristics and temperature distribution are simulated and compared to those of bulk and standard silicon-on-insulator (SOI) MOSFETs. The SOAN devices are shown to have good leakage and subthreshold characteristics. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOAN can mitigate the self-heating penalty effectively. Our study suggests that AlN is a suitable alternative to silicon dioxide as the buried dielectric in SOI, and expands the applications of SOI to high temperature.     

A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs     

Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current

This paper estimates the off-leakage current (I/sub off/) and drive current (I/sub on/) of various SOI MOSFETs by simulations based on the hydrodynamic-transport model; the band-to-band tunneling (BBT) effect at the drain is taken into consideration. Here, the simulations are done for SOI structures with a thick channel where the distinct quantization of energy is irrelevant to the present results. It is shown that merging hydrodynamic transport with the BBT effect is indispensable if realistic I/sub off/ estimates are to be achieved. It is shown that the symmetric double-gate SOI MOSFET does not always offer better drivability than other SOI MOSFETs, and that a single-gate SOI MOSFET with carefully selected parameters exhibits superior performance to double-gate SOI MOSFETs. It is also demonstrated that the quantum tunnel current is not significant, even in 20-nm channel SOI MOSFETs. The results suggest that we can still employ the conventional semi-classical method to estimate the off-leakage current of sub-100-nm channel low-power SOI MOSFETs.     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Hot-carrier effects and lifetime prediction in off-state operationof deep submicron SOI N-MOSFETs

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V_t variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V_d range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V_d, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability