Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Thermal and flicker phase noise analysis in rotary traveling-wave oscillator

This paper analyzes the thermally induced phase noise and the up-conversion of flicker noise into phase noise of rotary traveling-wave oscillator (RTWO). Based on the analyses, this paper extracts the closed-form formulas for the thermal and flicker phase noise of the RTWO. This paper compares the theoretical results with appropriate simulations to evaluate the accuracy of the derived closed-form formulas. Comparisons confirm the accuracy of the extracted phase noise formulas. By using the presented straightforward approach along with accurate phase noise formulas, the designers can understand the RTWO ' s design tradeoffs. Also, they can design the RTWO for a specific phase noise without needing lengthy simulations.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

Mode dynamics in fourth‐order LC oscillators

We present a complete analysis of single and concurrent modes in fourth‐order LC‐voltage‐controlled oscillators ( VCOs), which are increasingly applied in dual‐band communication systems. We give a procedure based on the averaging method that simplifies the derivation of the abridged equations, which are derived without resorting to a change of co‐ordinates. The amplitudes of the oscillatory modes in steady state and in transient are found in explicit form. Conditions for the stability of the single and concurrent modes are derived, which apply to any active one‐port dual‐band LC‐VCO and allow one to predict the nonlinearities ensuring the occurrence of a stable concurrent mode. Numerical and experimental results show a good accuracy of the presented formulas. Copyright © 2016 John Wiley & Sons, Ltd.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

Evaluation and comparison of GHz‐range LC oscillators using time‐varying root‐locus

This paper presents a comprehensive comparison between complementary metal‐oxide‐semiconductor (CMOS) LC‐oscillator topologies often used in GHz‐range transceivers. The comparison utilizes the time‐varying root‐locus (TVRL) method to add new insights into the operation of different oscillators. The paper focuses on the treatment of the TVRL trajectories obtained for different oscillators and establishes links between the trajectories and physical phenomena in oscillators. The evaluation of the root trajectories shows the advantages of the TVRL method for comparing oscillator topologies, which is also extended towards the analysis of voltage‐controlled oscillators. The necessary circuit simplifications required in closed‐form root‐locus analysis are avoided by the TVRL, which allows precise oscillator comparison and reveals details on the topology specifics. The derived conclusions have been verified by the Cadence Spectre‐RF simulator on 130‐nm CMOS process. Copyright © 2011 John Wiley & Sons, Ltd.     

Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

Channel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, γ, of NMOS is 3.5 for 40‐nm gate length, 2.0 for 90‐nm gate length in spite of being ⅔ for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using γ=⅔ because the part of noise performance of VCO gain‐cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted. Copyright © 2005 John Wiley & Sons, Ltd.     

Time‐domain analysis of phase‐noise and jitter in oscillators due to white and colored noise sources

This paper presents an original time‐domain analysis of the phase‐diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase‐noise and jitter and provides useful design‐oriented closed‐form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.     

Phase noise analysis of source injection coupled quadrature oscillator

This paper analyzes the thermally induced phase noise and the up-conversion of flicker noise into phase noise of source injection coupled quadrature oscillator (SIC-QOSC), for the first time. Furthermore, this paper provides a complete analysis for the injection current of the SIC-QOSC and extracts the closed-form expressions for it for the first time, too. These expressions lead to obtaining the harmonics of the injection current as well as the oscillation amplitude, which is necessary for the phase noise analysis. To evaluate the extracted equations, this paper compares the calculated results with appropriate simulations. Comparisons confirm the accuracy of the proposed injection current expressions and the phase noise formulas. Using the closed-form equations of phase noise, designers can understand the SIC-QOSC's design tradeoffs and design the oscillator for given phase noise.     

ADF4350低相噪频率合成器在射频无线通信设备中的应用

现代射频和微波电子系统中要求频率源具有高频低相噪,且具有可靠性好、体积小、功耗低的特点。ADF4350频率合成器具有全集成、低相位噪声的优点,内置片上VCO（压控振荡器）与PLL（锁相环）,可以工作在极宽的连续频率范围内,广泛用于无线基础设备及测试设备,无线LAN,CATV和时钟发生器中。本文简要介绍了ADF4350的主要功能,详细给出了基于ADF4350用作直接变换调制器以及和ADuC812,ADSP-21xx的接口连接的设计方案。     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

On the simulation of fast settling charge pump PLLs up to fourth order

In this paper, we discuss three different models for the simulation of integer‐N charge‐pump phase‐locked loops (PLLs), namely the continuous‐time s‐domain and discrete time z‐domain approximations and the exact semi‐analytical time‐domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time‐domain model are introduced and the results are compared with those obtained by means of the s‐domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB‐OFDM UWB systems. Copyright © 2010 John Wiley & Sons, Ltd.     

Modeling of unbalanced three‐phase driving‐point impedance with application to control of grid‐connected power converters

The dq transformation is widely used in the analysis and control of three‐phase symmetrical and balanced systems. The transformation is the real counterpart of the complex transformations derived from the symmetrical component theory. The widespread distributed generation and dynamically connected unbalanced loads in a three‐phase system inherently create unbalanced voltages to the point of common coupling. The unbalanced voltages will always be transformed as coupled positive‐sequence and negative‐sequence components with double‐frequency ripples that can be removed by some filtering algorithms in the dq frame. However, a technique for modeling unbalanced three‐phase impedance between voltages and currents of same sequences or of opposite sequences is still missing. We propose an effective method for modeling unbalanced three‐phase impedance using a decoupled zero‐sequence impedance and two interacting positive‐sequence and negative‐sequence balanced impedances in the dq frame. The proposed method can decompose a system with unbalanced resistance, inductance, or capacitance into a combination of independent reciprocal bases (IRB). Each IRB basis belongs to one of the positive‐sequence, negative‐sequence, or zero‐sequence system components to facilitate further analysis. The effectiveness of this approach is verified with a case study of an unbalanced load and another case study of an unbalanced voltage compensator in a microgrid application. Copyright © 2015 John Wiley & Sons, Ltd.