A generalized family of memristor‐based voltage controlled relaxation oscillator

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage‐controlled memristor‐based relaxation oscillator including two memristors is presented. The operation of two memristors‐based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a closed form is introduced for each case. The effect of changing the circuit parameters on the oscillation frequency and conditions is investigated numerically. In addition, the derived equations are verified using several transient PSPICE simulations. The power consumption of each oscillator is obtained numerically and compared with its PSPICE counterpart. Furthermore, controlling the memristive oscillator with a voltage grants the design an extra degree of freedom which increases the design flexibility. The nonlinear exponential model of memristor is employed to prove the oscillation concept. As an application, two examples of voltage‐controlled memristor‐based relaxation oscillator are provided to elaborate the effect of the reference voltage on the output voltage. This voltage‐controlled memristor‐based relaxation oscillator has nano size with storage property that makes it more efficient compared with the conventional one. It would be helpful in many communication applications.     

SPICE modeling of nonlinear memristive behavior

The recent discovery of the ‘modern’ memristor has drawn great attention of both academia and industry. Given their favorable performance merits, memristors are expected to play a fundamental role in electronic industry. Modeling of memristive devices is essential for circuit design, and a number of Simulation Program with Integrated Circuit Emphasis (SPICE) models have already been introduced. The common problem in most models is that there is no threshold consideration; hence, only a few address the nonlinear nature of the device. This paper aims to present a SPICE implementation of a threshold‐type switching model of a voltage‐controlled memristive device that attributes the switching effect to a tunneling distance modulation. Threshold‐type switching is closer to the actual behavior of most experimentally realizable memristive systems, and our modeling approach addresses the issue of programming thresholds. Both the netlist and the simple schematic are provided, thus making it easy to comprehend and ready to be used. Compared with other modeling solutions, it involves significantly low‐complexity operation under an unlimited set of frequencies, and its simulation results are in good qualitative and quantitative agreement with the theoretical formulation. The proposed model is used to simulate an antiserial memristive switch, proving that it can be efficiently introduced in complex memristive circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Some invariant sums of higher‐order sensitivities

In this paper, a new class of invariant sensitivity sums of higher‐order sensitivities is given. Sensitivity sums considered are relevant to a network function of general lumped time‐invariant circuits containing passive and active elements. It is assumed that the circuit is linear and consists of one‐port elements and two‐port elements only. A part of the one‐port elements is described by admittance parameters and the other part by impedance parameters. The rest of the one‐port elements are independent sources. Two‐port elements are only controlled sources. Hybrid matrix should describe functional relationships of the elements. Formulas for invariant sums of sensitivities of first, second, third, and fourth order are presented. Copyright © 2008 John Wiley & Sons, Ltd.     

Second order mem‐circuits

This paper presents a comprehensive taxonomy of so‐called second‐order memory devices, which include charge‐controlled memcapacitors and flux‐controlled meminductors, among other novel circuit elements. These devices, which are classified according to their differential and state orders, are necessary to get a complete extension of the family of classical nonlinear circuit elements (resistors, capacitors, and inductors) for all possible controlling variables. Using a fully nonlinear formalism, we obtain nondegeneracy conditions for a broad class of second‐order mem‐circuits. This class of circuits is expected to yield a rich dynamic behavior; in this regard, we explore certain bifurcation phenomena exhibited by a family of circuits including a charge‐controlled memcapacitor and a flux‐controlled meminductor, providing some directions for future research. Copyright © 2014 John Wiley & Sons, Ltd.     

Memristor‐based voltage‐controlled relaxation oscillators

This paper introduces two voltage‐controlled memristor‐based reactance‐less oscillators with analytical and circuit simulations. Two different topologies which are R‐M and M‐R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor‐based voltage‐controlled oscillator (VCO) is introduced as an application for the proposed circuits which is nano‐size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.     

Generation and classification of CCII and ICCII based negative impedance converter circuits using NAM expansion

A new simplified generation method of negative impedance converter circuits (NIC) is introduced. The generation method is based on nodal admittance matrix expansion starting from the input admittance of the NIC circuit terminated by a load rather than treating the NIC as a two‐port network element. The four pathological elements, namely nullator, norator, voltage mirror and current mirror, are used in the generation procedure. Two classes of the NIC pathological circuits are defined; each class includes two types. Eight pathological NIC circuits are generated for each class. Two alternative current conveyor and inverting current conveyor‐based realizations for each pathological circuit based on alternative pairing of the pathological elements are defined resulting in a total of 16 NIC circuit for each class and a total of 32 NIC circuits. A new NIC‐based circuits realizing floating negative impedances are also introduced. Copyright © 2010 John Wiley & Sons, Ltd.     

A memristive dual-slope A/D converter

As an emerging device, memristor has several excellent properties like changeable memristance, nonvolatility, and nanoscale. Based on complementary metal-oxide-semiconductor (CMOS) dual-slope analog-to-digital (A/D) converter, this paper proposes a memristive dual-slope A/D converter. Owing to the usage of memristor, the proposed memristive A/D converter not only has more compact circuit structure and simpler control timing than the CMOS one but also has advantages over the existing memristive conversion circuits in circuit design and application. For the memristive A/D converter, a conversion process consists of two count procedures. By means of controlling the memristance change in the two count procedures, the A/D converter converts an analog signal to the corresponding digital count value. Meanwhile, the conversion result is inferred according to the circuit structure of the A/D converter. Then, combining the conversion process and PSPICE simulation, this paper analyzes the anti-interference performance of the A/D converter. Further, the robustness of the A/D converter is presented, applying the similar analysis methods. The analysis results demonstrate that the proposed A/D converter has good anti-interference and robustness performances.     

High‐order sensitivity invariants

The aim of the research reported in this paper is to extend the notion of invariant sensitivity sum, widely known for electrical networks, from first‐order sensitivities to high‐order sensitivities. The results are high‐order invariant sums of sensitivities of the first and the second kind, formulated for nonlinear lumped circuit, which consists of one‐port and two‐ports only. One‐ports are generalized resistances, capacitances, inductances, voltages, and current sources, whereas two‐ports are nonlinear generalizations of four types of controlled sources. It is observed that the invariant sums actually found for nonlinear lumped networks are generalizations of sums given earlier by authors for linear lumped networks. The article is illustrated by numerical sensitivity analysis of simple linear and nonlinear circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

Modeling the memristor with piecewise linear function

Memristor is introduced as the fourth basic circuit element. In this paper, we show that piecewise linear function can be used to model memristor. Piecewise linear function is used as a window function to model the memristor device. The piecewise linear window function is linear at each subregion of the domain. Because of this good character, explicit relation between the thickness of the doped region and the charge can be delivered, together with the explicit memristance expression. Models using a general nonlinear window function may not have these explicit results. The piecewise linear window function is also more flexible than the existing window functions. Piecewise linear function can also be used to model the more general memristive systems. Copyright © 2014 John Wiley & Sons, Ltd.     

All‐pass sections with rich cascadability and IC realization suitability

In this paper, two new circuit configurations for realizing voltage‐mode (VM) all‐pass sections (APSs) are presented. The proposed circuits employ only two differential voltage current conveyors (DVCCs) and are cascadable with other VM circuits due to their high‐input and low‐output impedances. The first configuration uses a grounded resistor and a grounded capacitor without requiring matching constraints, whereas the second employs two grounded resistors and a grounded capacitor with a single matching condition. While the first configuration can realize only one all‐pass response, the second can provide inverting and non‐inverting all‐pass responses with selection of appropriate input port. Adding two grounded resistors to the proposed filters, variable gain APSs can also be obtained. As applications, two quadrature oscillators, each of which using one of the proposed all‐pass circuits, one grounded resistor and one grounded capacitor are presented. SPICE simulation results are included to verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.     

链式STATCOM直流侧电压平衡控制策略研究

针对STATCOM电容直流电压不稳定问题进行了分析,提出了一种增加附加充放电电路方式的STATCOM电容电压控制策略。采用附加电路对链式STATCOM电容进行充电及稳压控制,其中附加电路多绕组变压器的使用,有效地隔离了附加电路各链节直接的电的联系,消除了附加电路和装置主电路同时投入时电压瞬时降为零的现象,使得附加电路的控制策略可以完全和主电路控制策略独立;附加电路既可以直接接到大电网中,也可以采用与电网分离的独立供电电源,甚至可以采用大容量的UPS,可以较好地实现装置启动、快速功率切换等。装置动态响应能力亦有所增强,同时当主电路出现较大电压波动时,仍可以保证STATCOM电容电压的稳定,正常地输出无功。     

Novel chaotic behavior in the Muthuswamy–Chua system using Chebyshev Polynomials

In this paper, three kinds of memristors with memristance functions obtained from the Chebyshev polynomials are used in the Muthuswamy–Chua system, which has only three circuit elements: a linear passive inductor, a linear passive capacitor and a nonlinear active memristor. We use multivariable second‐order polynomial functions of current and memristor state for the internal state function of the memristor. This enables our system to generate not only double‐scroll but also four‐scroll attractors. Systematic studies of chaotic behavior in these systems are performed using phase portraits, bifurcation diagrams and Lyapunov exponents. Simulation results show that all these systems exhibit chaotic behavior over a range of control parameters. Copyright © 2014 John Wiley & Sons, Ltd.     

Formulating hybrid equations and state equations for nonlinear circuits using SPICE

Hybrid equations are often used in the theoretical study of nonlinear resistive circuits because they have an easy‐to‐analyze structure. They are also advantageous in the numerical analysis of nonlinear resistive circuits because they are separable and consist of a relatively small number of variables. However, the hybrid equations are seldom used in practical applications because their formulation is complicated. In this letter, we propose a simple method for formulating the hybrid equations using SPICE. In the proposed method, we only perform the transient analysis of SPICE on a linear circuit that is obtained through a small modification to the original circuit. It is also shown that state equations for nonlinear dynamic circuits can also be formulated by using the proposed method. Copyright © 2011 John Wiley & Sons, Ltd.     

Memristive computing devices and applications

Advances in electronics have revolutionized the way people work, play and communicate with each other. Historically, these advances were mainly driven by CMOS transistor scaling following Moore’s law, where new generations of devices are smaller, faster, and cheaper, leading to more powerful circuits and systems. However, conventional scaling is now facing major technical challenges and fundamental limits. New materials, devices, and architectures are being aggressively pursued to meet present and future computing needs, where tight integration of memory and logic, and parallel processing are highly desired. To this end, one class of emerging devices, termed memristors or memristive devices, have attracted broad interest as a promising candidate for future memory and computing applications. Besides tremendous appeal in data storage applications, memristors offer the potential to enable efficient hardware realization of neuromorphic and analog computing architectures that differ radically from conventional von Neumann computing architectures. In this review, we analyze representative memristor devices and their applications including mixed signal analog-digital neuromorphic computing architectures, and highlight the potential and challenges of applying such devices and architectures in different computing applications.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

An Equalization Time Reduction Method Using a Pseudo‐Random Number Sequence for a Cell Voltage Equalization Circuit with an LC Series Circuit

When the cells of energy storage devices such as electric double‐layer capacitors are connected in series, it results in voltage imbalance in each cell because of the nonuniform properties of the individual cells. In a previous research, the authors proposed a novel cell voltage equalization circuit using an LC series circuit, and they examined the effectiveness of this circuit. However, the characteristics of the cell voltage equalization operation depend on each cell voltage difference. Therefore, the proposed circuit has a disadvantage that the equalization time tends to be longer than other cell voltage equalization circuits with a boosting circuit. This paper proposes an equalization time reduction method that uses a pseudo‐random number sequence generated by the linear congruential generators. The proposed method can reduce the average equalization time without adding any other active or passive elements. The effectiveness of the proposed method is verified through the experimental results. According to the experimental results, the proposed equalization time reduction method reduces the equalization time to 86.5% of the conventional method.     

Improved static and dynamic performances of a two‐cell DC–DC buck converter using a digital dynamic time‐delayed control

Multi‐cell converters have been developed to overcome shortcomings in usual switching devices. The control system in these circuits is twofold: first, to balance voltages of the switches and second to regulate the load current to a desired value. However, with a purely proportional controller, the system presents a static error. With a PI controller the static error is annihilated, but at the expense of shortening the stability region and increasing settling time. In this work, a zero static error dynamic controller for a two‐cell DC–DC buck converter is designed. To achieve zero current error, we propose a generalized scheme of a dynamic controller. Then, using nonlinear analysis and Lyapunov stability theory and bifurcation prediction tools, we prove that zero static error is achieved. The proposed controller outperforms the PI controller in terms of settling time in the presence of saturating effect during the start‐up transients. Numerical simulations in the form of time domain waveforms and bifurcation diagrams from switched circuit‐based model are presented to confirm our theoretical results. Copyright © 2010 John Wiley & Sons, Ltd.     

电压切换回路的隐患分析

双母线接线方式下的主变和线路操作箱中都设有电压切换回路。电压切换继电器同时动作将会引起PT二次并列并烧毁PT二次保险,从而使全站保护装置失压的现象;双重故障下,甚至造成全站失压,扩大事故范围的严重后果。针对电压切换回路中存在的这种隐患,本文进行了详细的分析探讨,并提出了一些相应措施,以提高电压切换回路的可靠性以及变电站运行的可靠性。