Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

A family of bulk‐driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3‐0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain‐bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18‐μm n‐well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.     

A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and design of a high‐compliance ultra‐high output resistance current mirror employing positive shunt feedback

This paper reports a novel high‐compliance, very accurate and ultra‐high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra‐high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post‐layout simulations. Designed in the IBM 130‐nm standard CMOS process, the circuit consumes 230 × 110 µm² of silicon area. Post‐layout simulation results indicate that with a 3.3‐V power supply, output voltage compliance of 0.93V_Supply is achieved at a maximum output current of 96 μA. Moreover, an extremely ultra‐high output resistance of 320 GΩ is achieved, which is one of the highest reported values of output resistance for current mirrors implemented using regular CMOS technology. The ?3 dB upper cut‐off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 μA to the load. Copyright © 2014 John Wiley & Sons, Ltd.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

Low‐noise low‐power front‐end logarithmic amplifier for neural recording system

In this work, a low‐power, low‐noise logarithmic preamplifier for biopotential and neural recording application is presented. The amplifier is based on a linear limit logarithmic amplifier technique, and an active filter as a DC cancellation filter has been included to its input in order to eliminate DC offsets, which are produced at the electrode–tissue interface. This system has been simulated in a UMC standard 90‐nm 1P9M CMOS process. Five dual gain stages are used to produce the required linear limit logarithmic amplifier. The dynamic range of the amplifier is measured to be 48 dB which covers the signals with amplitude from 20 μV to 5 mV. The amplifier consumes 23.5 μW from a 1.2‐V power supply and has a maximum gain of 69.8 dB. The simulated input referred noise is 5.3 μV over 0.1 Hz to 20 kHz. Copyright © 2012 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A sub‐1V supply CMOS voltage reference generator

An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p‐n‐p substrate vertical bipolar devices and a voltage‐to‐current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter‐base voltage of the core p‐n‐p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail‐to‐rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/^°C in the range of ? 40 and 125^°C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of ? 36 and 125^°C. Copyright © 2011 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

Design of a low‐power high open‐loop gain operational amplifier for capacitively‐coupled instrumentation amplifiers

We present the design of a low‐power high open‐loop gain opamp for use in chopper‐stabilized capacitively coupled instrumentation amplifiers (CCIAs). The opamp utilizes the current‐reuse folded‐cascode topology and a low‐power gain‐boosting technique to maximize its power efficiency and open‐loop gain. The proposed technique is applied to the designs of two CCIAs: the conservative CCIA with a moderate current scaling ratio and the stringent CCIA with a very high current scaling ratio. Utilizing the current scaling ratio of 4:1, the conservative CCIA, designed and fabricated in a 0.18 μ m CMOS process, consumes a total current of 1.69 μ A from a 0.8‐V supply voltage and achieves a thermal noise floor of 56.5 nV/ . Utilizing the current scaling ratio of 38:1, the stringent CCIA, designed and simulated in a 0.13 μ m CMOS process, consumes a total current of 1.4 μ A and achieves a thermal noise floor of 48 nV/ . The proposed design technique should benefit the designs of low‐power instrumentation amplifiers in advanced processes in which channel‐length modulation and the limited current consumption and supply voltage make the designs of high open‐loop gain opamps difficult. Copyright © 2017 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

A power‐efficient 600‐mVpp voltage‐mode driver with independently matched pull‐up and pull‐down impedances

In this study, a large‐swing, low‐power voltage‐mode driver with independently matched pull‐up and pull‐down impedances is proposed. To achieve large swing and constant impedances during a transition, a P‐over‐N structure is implemented with regulators calibrating the impedances. Two regulators are dedicated to matching the pull‐up and pull‐down impedances by regulating the supply voltages of the driver and predriver, respectively. Because background impedance calibration loops are adopted to track the process, voltage, and temperature (PVT) variations, the proposed driver can operate properly without additional calibration time. To reduce the power consumption of the calibration loops, scaled replicas of the actual driver are used. Moreover, an analysis of design optimization for the proposed driver is presented. The proposed driver was fabricated in 65‐nm CMOS technology and verified at a 5‐Gb/s data rate. Measurement results show that the proposed driver has a voltage swing of 600 mV_pp and a horizontal eye opening of 0.5 UI. The prototype chip consumes 6 mW at a 1.0‐V supply. Copyright © 2014 John Wiley & Sons, Ltd.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.