A CCII‐based wide frequency range square waveform generator

In this paper, we propose a novel current‐mode solution suitable for the square waveform generation. The designed oscillator, which utilizes only two positive second‐generation current conveyors as active blocks, six resistors and a capacitor, is based on a current differentiation, instead of voltage integration, typical of developed solutions both in voltage‐mode and in current‐mode approaches, so avoiding circuit limitations due to the node saturation effects. The proposed circuit has been designed, as an integrated solution at transistor level, in a standard CMOS technology, with low‐voltage (± 1V) and low‐power (430µW) characteristics. Simulation results have confirmed the good circuit behaviour, also for working temperature drifts, showing good linearity in a wide oscillation frequency range, which can be independently adjusted through either capacitive (in the range pF ? µF) or resistive (in the range M Ω–G Ω) external passive components. Waiting for the chip fabrication, preliminary measurements have been performed using a laboratory breadboard employing the CCII with AD844 commercial component and sample capacitors and resistors. The experimental results have shown good agreement with both simulations and theoretical expectations. Copyright © 2011 John Wiley & Sons, Ltd.     

A fully electronically controllable Schmitt trigger and duty cycle‐modulated waveform generator

The paper introduces a new Schmitt trigger consisting of only one multiple‐output current inverting differential input transconductance amplifier with no passive element. The proposed circuit is simple and usable up to 100 MHz with the advantage of electronically controlled threshold levels and amplitude of the output. The circuit is also little sensitive to temperature and benefits from low power dissipation (0.5 mW). The amplitude of the output current is tunable electronically from 5 nA to 500 μA, which is a wide tunable range. The effects of transistors mismatch on proposed Schmitt trigger have also been explored. The utility of the proposed circuit is further justified through its application as a triangular/square wave generator, with a maximum frequency of 75 MHz. Duty cycle modulation through electronic means is also shown for the generator circuit, where duty cycle results for 80, 20, and 95% have been included, by varying external control current. The cadence VIRTUOSO simulation results by using generic process design kit 90‐nm technology are shown to confirm the proposed theory. The proposed circuits are also verified through experimental results by using commercial integrated circuits: AD844 and LM13700. All the simulated and experimental results promise potential applications of the proposed circuits in instrumentation and communication systems. Copyright © 2017 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

Common‐mode gain reduction technique and its applications

This paper proposes a common‐mode gain reduction technique and a new approach for a balanced‐type system design. Two design examples of a balanced‐type operational transconductance amplifier and a balanced‐type filter are given. The proposed scheme employs the proposed common‐mode gain reduction technique together with the common‐mode feedback (CMFB) network, which is used only to set a bias, to meet requirements of common‐mode rejection. Compared with the conventional method, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method shows reduction in design complexities and relaxation of the stability conditions. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A low distortion CMOS continuous‐time common‐mode feedback circuit

In high‐gain fully differential operational amplifier (FD op‐amp) design, the output common‐mode (CM) voltage of the FD op‐amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common‐mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous‐time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded‐cascode op‐amp and the other is the Multiply‐by‐Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog‐to‐digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

A new electro‐static micro‐generator for energy harvesting from diaphragm muscle

In this paper, we propose a new energy scavenging system for powering bio‐implantable devices. Different available energy sources and micro‐generators are examined. The operation of electrostatic generators will be examined in detail, and their design issues are discussed. The proposed generator is analyzed, and a closed form formula is developed for the capacitor voltages. Also, an equation is obtained for the output power for the proposed circuit. It will be shown that the diaphragm muscle in conjunction with the electrostatic micro‐generator can be used to extract energy from human body. The diaphragm muscle has a continuous movement with a relatively fixed frequency. There is enough space around this muscle to place the micro‐generator. Using the proposed system, it will be shown that it is possible to produce 230 mW power in a 125 mm³ volume from the diaphragm muscle. Copyright © 2017 John Wiley & Sons, Ltd.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

A digitally‐assisted constant‐on‐time dynamic‐biasing (COT‐DB) technique has been proposed to enable significant enhancement in dynamic performances, while the average current consumption can be kept to ultralow level. This dynamic‐biasing technique has a predefined magnitude and duration on biasing current boost, which is beneficial to estimate power budget in systems with finite energy source. The proposed technique has been applied to a low‐dropout regulator (LDO) to demonstrate the effectiveness. Experimental results show that significant improvements in settling times during load‐transients and line‐transients are as much as 880×, while the current consumption is only 1.02 μA. In fact, for the same dynamic performances, the average current consumption of LDO with COT‐DB technique can be as low as 0.39% of the LDO with heavy static biasing. The digitally‐assisted implementation of the technique also allows robust augmentation of the technique onto almost all analog systems. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel induction generator system using bi‐directional PWM converter for small‐scale power applications

This paper presents a deadbeat current control structure for a bidirectional power flow pulse‐width modulation (PWM) converter connected to a stand‐alone induction generator (IG), which works with variable speed and different types of loads. Sensorless control of the IG, meaning stator voltage vector control without a mechanical shaft sensor, is considered to regulate both the IG line‐to‐line voltage and the DC‐bus voltage of the PWM converter. In the proposed system, a newly designed phase locked loop (PLL) circuit is used to determine the stator voltage vector position of the IG. A 2.2 kW laboratory prototype has been built to confirm the feasibility of the proposed method. The proposed cost‐effective IG system with a deadbeat current‐controlled PWM converter and capacitor bank requires only three sensors. Moreover, the required rating of the PWM converter becomes smaller due to the existence of the capacitor bank. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A new variable‐speed,constant‐frequency,stand‐alone power generating system

Variable‐speed and constant‐frequency power generating systems using rotor excitation of the wound‐rotor induction machines have been used for such applications as variable‐speed pump generators and flywheel energy storage systems. However, the stand‐alone generating system of this type has only been reported and has not yet been practically used. On the other hand, the stand‐alone generating systems using diesel engines have been widely used for emergency supplies of plants or isolated islands and so on. However, in these cases, synchronous generators are usually used. If the output frequency is to be kept constant, there is the need to control the speed of the engine using a high‐performance governor. Even then, the output frequency changes in the case of a sudden load change. This paper proposes a new stand‐alone power generating system. In this system, the constant‐frequency output voltage can be obtained even though rotor speed changes by several percent. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 146(2): 75–85, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10191     

A battery charger with maximum power point tracking function for low‐power photovoltaic system applications

A battery charger with MPPT function for low‐power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high‐frequency operation. Some current‐sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high‐frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.     

A sub‐1V supply CMOS voltage reference generator

An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p‐n‐p substrate vertical bipolar devices and a voltage‐to‐current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter‐base voltage of the core p‐n‐p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail‐to‐rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/^°C in the range of ? 40 and 125^°C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of ? 36 and 125^°C. Copyright © 2011 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

A fully‐integrated CMOS UWB transceiver for ultra‐low‐power short‐range application

In short‐range UWB communication systems, the low‐power design is the most important issue to make UWB technology attractive. A novel trigger receiving algorithm for UWB signals is proposed, which can reduce the system power significantly at the cost of slight performance degrade. A UWB transceiver based on the trigger receiving algorithm is designed and fabricated in HJTC 0.18 µm CMOS process with a total size of 0.45 mm². The experimental results show that the total power consumption of the transceiver is only 12 mW at 100 Mb/s data rate from a 1.8 V supply, making it suitable for low‐power short‐range communication. Copyright © 2010 John Wiley & Sons, Ltd.     

A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.