Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

This paper reports the analyses of the inductive degeneration , noise filter , and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd.     

Suppression of overtone oscillation and low‐current operation using novel‐design scheme for quartz crystal oscillators

A novel design is proposed for a low‐frequency quartz crystal oscillator circuit. Negative resistance in a low‐frequency CMOS‐inverter quartz oscillator was reviewed for the fundamental mode at 32 kHz and the overtone oscillation at 200 kHz. Suppression of the overtone oscillation, appropriate gain, and drive current reduction are realized by adding only three circuit components. Experimental results and an estimate of the absolute value of the negative resistance are presented for the conventional Colpitts circuit and two types of the quartz crystal oscillator circuit. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Phase noise analysis in CMOS differential Armstrong oscillator topology

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Four‐segment oscillator circuit for piezoelectric sensing devices

Novel circuit design is proposed for a low‐frequency quartz crystal oscillator circuit that consists of four segments. The characteristics of the negative resistance in a low‐frequency Complementary Metal Oxide Semiconductor (CMOS)‐inverter quartz oscillator were reviewed for the two modes of SC (stress‐compensated) cut mode and the overtone of low‐frequency mode; separation of two modes and suppression of overtone oscillation were demonstrated successfully. Experimental results and an estimate of the absolute value of the negative resistance are presented for the four‐segment oscillator circuit and the conventional Colpitts circuit and two new types of oscillator circuits. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Electronically controlled oscillator with linear frequency adjusting for four‐phase or differential quadrature output signal generation

This paper introduces novel four‐phase oscillator employing two Dual‐Output Controlled Gain Current Follower Buffered Amplifiers (DO‐CG‐CFBAs), single Current Amplifier, three resistors, and two grounded capacitors suitable for differential quadrature signal production (floating outputs). To control the frequency of oscillation (FO) and condition of oscillation (CO), only the current gain adjustment of active elements is used. The circuit was designed by well‐known state variable approach. The oscillator employs three active elements for linear control of FO and to adjust CO and provides low‐impedance voltage outputs. Furthermore, two straightforward ways of automatic amplitude gain control were used and compared. Active elements with very good performance are implemented to fulfill required features. Suitable CMOS implementation of introduced DO‐CG‐CFBA was shown. Important characteristics of the designed oscillator were verified experimentally and by PSpice simulations to confirm theoretical and expected presumptions. Copyright © 2013 John Wiley & Sons, Ltd.     

Sinusoidal shaping of the ISF in LC oscillators

A new method to decrease the phase noise of the sinusoidal oscillators is proposed. The proposed method is based on using a dynamic transistor biasing in a typical oscillator topology. This method uses the oscillator impulse sensitivity function (ISF) shaping to reduce the sensitivity of the oscillator to the transistor noise and as a result reducing the oscillator phase noise. A 1.8 GHz, 1.8 V designed oscillator based on the proposed method shows a phase noise of ?130.3dBc/Hz at 1 MHz offset frequency, thereby showing about 6 dB phase noise decreasing in comparison with the typical constant bias topology. This result is obtained from the simulation based on 0.18u CMOS technology and on‐chip spiral inductor with a quality factor equal to 8. Copyright © 2007 John Wiley & Sons, Ltd.     

High output impedance CMQOs using DVCCs and grounded components

In this paper a new circuit topology for realizing second‐order current‐mode quadrature oscillator is proposed. Three additional circuits are further derived from it, thus resulting in four distinct circuits. Each circuit employs three differential voltage current conveyors and all grounded passive components, ideal for IC implementation. All the circuits possess high output impedance. The circuits exhibit non‐interactive frequency control and low THD. The effects of non‐idealities are also analyzed. PSPICE simulations using 0.5 µCMOS parameters confirm the validity and practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

Low Phase Noise LC-VCO with Multi-Stage Filtering

A low-phase-noise CMOS voltage-controlled oscillator (VCO) with zero-bias scheme and multi-stage filtering is presented. Sharing ground with fully integrated loop filter, the PMOS-only VCO achieves a zero-bias scheme, which prevents tuning line noise from disturbing VCO output common-mode voltage and hence minimizes phase noise caused by nonlinear C-V characteristic of varactors. Top-biased current source is optimized by multi-stage filtering to reduce 1/f flicker and thermal noise. Fabricated in TSMC 180 nm CMOS process, the proposed VCO exhibits a measured oscillation frequency of 0.85~1.45 GHz, with a phase noise of -121.8~-131.3 dBc/Hz @1MHz offset over the whole band. Power consumption is 3.8~6.3mW from a 1.8V supply.     

Short‐term stability in the intermediate region between quartz crystal oscillation and LC oscillation

In a quartz crystal oscillator circuit, an LC resonance circuit was inserted that enabled major enlargement of the variable range of frequency compared with the conventional Colpitts or Pierce quartz crystal oscillator. The short‐term stability of the oscillation was measured with Allan variance in the intermediate region between the quartz resonance and LC resonance, showing higher stability compared with the common LC oscillator. The analytical result is presented showing continuous transition from the quartz resonance to the LC resonance. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Memristor‐based voltage‐controlled relaxation oscillators

This paper introduces two voltage‐controlled memristor‐based reactance‐less oscillators with analytical and circuit simulations. Two different topologies which are R‐M and M‐R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor‐based voltage‐controlled oscillator (VCO) is introduced as an application for the proposed circuits which is nano‐size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.     

A 3.6‐mW 6‐GHz current‐reuse VCO‐buffer with improved load drivability in 65‐nm CMOS

A new current‐reuse voltage‐controlled oscillator (VCO)‐buffer with enhanced load drivability is proposed. It incorporates a PMOS‐based source follower stacked atop a NMOS‐based LC VCO to share the bias current, while preventing the voltage stress at any oscillation node from exceeding the 1.2‐V technology voltage limit. Also, ac‐coupling networks are avoided between the VCO and buffer, improving the Q of the LC tank while minimizing parasitics. With internal buffering, the VCO can directly drive up a 50‐Ω load for testing, or to withstand a large capacitive load in on‐chip local oscillator distribution, particularly suitable for multi‐band MIMO WLAN radios . The fabricated VCO‐buffer in 65‐nm CMOS measures 13.8% tuning range from 5.64 to 6.4 GHz, consumes 3.6 mW at 1.2 V and exhibits ?108.84 dBc/Hz phase noise at 1‐MHz offset. Copyright © 2013 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

低谐波失真的CMOS正弦波振荡器设计

本文设计了一种具有低谐波失真输出的CMOS正弦波振荡器.该振荡器以RC有源微分电路作为选频回路.在实际电路设计中应计及运算放大器的频率特性,由此可得RC有源微分电路为二阶高Q电路.该电路具有良好的选频特性,大幅降低了振荡器输出的谐波失真,并配合移相和可变增益电路以满足振荡器起振条件.使用本文设计的CMOS运算放大器,该振荡器可起振的带宽可达200 Hz~2 MHz,其谐波失真小于通带噪声.以输出正弦波频率为100 kHz为例,给出了Hspice仿真结果.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

微波Colpitts混沌电路在无线传输系统中的应用

Colpitts混沌振荡电路由单一的晶体三级管及其它线性元器件构成,是研究及应用非常广泛的三点式振荡电路。Colpitts混沌振荡电路能够产生各种不同频率的混沌信号,可以应用于无线传输、通信加密、信号检测等多个领域。介绍了两种类型的Colpitts混沌振荡器电路,并分析了其电路模型。同时将所产生的混沌振荡信号进行了对比、分析,并将其产生的混沌信号作为无线传输系统的激励信号。此外,互补累积分布函数曲线表明,以改进型的Colpitts混沌振荡电路所产生的混沌信号作为激励信号的无线电力传输系统具有更好的整流电路转换效率。最后,这些电路的转换效率的详图已被证明。     

1.2 V Sinh‐Domain allpass filter

A first‐order Sinh‐Domain allpass filter topology is introduced in this paper. It is constructed from a class‐AB current mirror and appropriately configured non‐linear transconductor cells. Due to the inherent class‐AB nature of Sinh‐Domain filters, the proposed topology offers the capability for handling currents at levels greater than that of the dc bias current level. Also, it offers the well‐known features of companding filters such as electronic adjustment of its frequency characteristics and the capability for operation in a low‐voltage environment. In addition, a four‐phase sinusoidal oscillator design example has been provided. The behaviour of the proposed topology has been evaluated and compared with other already known configurations, where the most important performance factors have been considered. Copyright © 2013 John Wiley & Sons, Ltd.