A transient‐improved low‐dropout regulator with nested flipped voltage follower structure

In this article, the existing low‐dropout regulator (LDO) based on cascoded flipped voltage follower (CAFVF) is reviewed. A new method to simulate the open‐loop gain of an LDO with a CAFVF structure is conveyed. The drawback of CAFVF‐based LDO is that the nondominant pole locates at low‐frequency and pole‐zero cancellation using a large equivalent series resistance of loading capacitor is required for stability. To tackle this problem, a novel LDO structure based on a nested CAFVF is proposed and analyzed in this article. It is shown that the nondominant pole is pushed to a high frequency and the LDO stability is improved. The proposed circuit is fabricated using a commercial 0.35‐µm CMOS technology, and the load‐transient response between 0.5 and 60 mA settles at approximately 5 µs. Copyright © 2012 John Wiley & Sons, Ltd.     

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

A digitally‐assisted constant‐on‐time dynamic‐biasing (COT‐DB) technique has been proposed to enable significant enhancement in dynamic performances, while the average current consumption can be kept to ultralow level. This dynamic‐biasing technique has a predefined magnitude and duration on biasing current boost, which is beneficial to estimate power budget in systems with finite energy source. The proposed technique has been applied to a low‐dropout regulator (LDO) to demonstrate the effectiveness. Experimental results show that significant improvements in settling times during load‐transients and line‐transients are as much as 880×, while the current consumption is only 1.02 μA. In fact, for the same dynamic performances, the average current consumption of LDO with COT‐DB technique can be as low as 0.39% of the LDO with heavy static biasing. The digitally‐assisted implementation of the technique also allows robust augmentation of the technique onto almost all analog systems. Copyright © 2015 John Wiley & Sons, Ltd.     

A low‐dropout voltage regulator with active current amplifier frequency compensation

This paper presents a new compensation scheme of low‐dropout regulator (LDO) design over the conventional methodology. With only 0.3 pF on‐chip compensation capacitor, a left‐half‐plane zero is realized within the regulation loop unity‐gain bandwidth and over 56 ^° phase margin is achieved under the full range of the load current. The LDO thus achieves stability without using the equivalent series resistance of the capacitor. It is proven experimentally that the proposed LDO has many attractive features such as high accuracy, low quiescent current, and smaller compensation capacitor. The measurement results show that the excellent performance can be comparable with the state of the art LDOs. Copyright © 2010 John Wiley & Sons, Ltd.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

New designs of low/high‐pass and mid‐pass/stop FIR digital filters

New designs of highly efficient low/high‐ and mid‐pass/stop (centre‐symmetric band‐pass/stop) FIR non‐recursive digital filters are presented. The designs are based on the modulation property of DFT, applied to the already presented MAXFLAT halfband low‐pass filters. The presented filters have explicit formulas for their tap‐coefficients, and therefore are very easy to design. They have highly smooth frequency response and wider transition regions like MAXFLAT filters. The design formulae are modified to give new classes of low/high‐ and mid‐pass/stop filters, for which, like in equiripple filters, the transition bandwidth can be reduced by increasing the size of ripple on magnitude response. It is shown, with the help of design examples, that the performance of these filters is comparable to that of equiripple filters. Copyright © 2001 John Wiley & Sons, Ltd.     

A novel low‐spur DDFS utilizing the twice second‐order high‐pass error feedback architecture

In this paper, the twice second‐order high‐pass error feedback (EF) (twice second‐order high‐pass EF (HPEF)) utilizing re‐feedback process and phase‐bit splitting technique in the second‐order HPEF to design a simplified low‐spur direct digital frequency synthesizer is proposed. The proposed method performs phase‐bit splitting technique and re‐feedback process in order to make the phase change tremendously and scramble the periodicity of the phase sequences violently in the original feedback path. In addition, the noise spectrum power is spread more uniformly in order to effectively suppress the spurs due to phase‐truncated error effect. Thus, the twice second‐order HPEF is implemented on a field programmable gate array development board, the Altera Stratix II EP2S60. The simulation and experimental results show that the proposed method can effectively achieve better spectrum performance, such as spurious‐free dynamic range, as compared to basic phase truncation, first‐order HPEF and second‐order HPEF architectures. Copyright © 2012 John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

Output‐voltage feedback control topology for inverters dedicated to renewable energy systems

We present a new control topology for inverters, mainly dedicated to renewable energy applications. The originality is due to the integration in the inverter of an adaptive regulation of its output voltage controlled by a closed feedback loop allowing compensating the voltage drops induced by load variations. The feedback control is based on an adaptive pulse wave modulation (APWM) technique, that controls the power switches of the inverter to obtain the purest possible sine‐wave voltage. The APWM technique straightforwardly compares the inverter output voltage with a reference signal at the grid frequency. In this contribution, this technique is applied to a single‐phase push‐pull inverter but could have been integrated for the control of all kinds of inverter topologies in renewable energy systems. We have shown that the APWM technique allows generating pure sine‐wave voltage, with low total harmonic distortion compared with the generally obtained by classical systems and that load variations do not affect the quality of the output. An experimental prototype of a single‐phase inverter with an adaptive regulation based on APWM technique was developed. The experimental characterizations of the prototype confirm the simulations. Copyright © 2017 John Wiley & Sons, Ltd.     

CMOS‐controlled inverting CDBA with a new all‐pass filter application

In this study, new active elements called inverting current differencing buffered amplifier (ICDBA) and current‐controlled ICDBA (C‐ICDBA) are presented. Unlike current differencing buffered amplifier (CDBA), their voltage transfer ratio between the Z and W terminals are equal to minus one. Furthermore, CMOS implementations of the C‐ICDBA and current‐controlled CDBA (C‐CDBA) are shown. Moreover, a novel first‐order all‐pass filter is proposed to show advantages and new circuit producing capability of the ICDBA/C‐ICDBA. Lastly, an electronically tunable band‐pass filter is given as an application example using the presented all‐pass filter. The measured and simulation results are in good agreement with the theoretical ones. Copyright © 2010 John Wiley & Sons, Ltd.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

Figures‐of‐merit genetic extraction for InGaAs lasers,SiGe low‐noise amplifiers,and ZnSe/Ge/GaAs HBTs

In this paper, we have successfully developed an intellectual parameter‐extraction methodology on the basis of a genetic algorithm (GA), involving the efficient search‐space separation and local‐minima‐convergence prevention schemes. Via an evolutionary simulation tool complemented with appropriate analytic equations, the enhanced approach has been applied to determine the significant figures‐of‐merit (FoMs), including internal quantum efficiency (η_i) as well as transparency current density (J_tr) of semiconductor lasers, minimum noise figure (NF_min) as well as associated available gain (G_A,assoc) of low‐noise amplifiers (LNAs), and DC as well as AC characteristics of heterojunction bipolar transistors (HBTs). For the first time, demonstrated FoM‐extraction results, which coincide well with the actually measured data, for state‐of‐the‐art InGaAs quantum‐well lasers, advanced SiGe LNAs, and abrupt ZnSe/Ge/GaAs HBTs are simultaneously presented to validate this multi‐parameter analysis and robust optimization. Copyright © 2011 John Wiley & Sons, Ltd.     

A novel method to improve low‐voltage ride‐through capability of wind turbine generators

With increasing penetration of wind farms, power grids have responded by developing specific grid codes to maintain their stability. One of the main grid codes is the low‐voltage ride‐through (LVRT) capability, which requires the wind generator to remain connected when the grid voltage sags for a certain time period. A wind farm with squirrel cage induction generators suffers this LVRT problem the most because of their direct connection to the grid and reactive power consumption. In this paper, a new method is proposed to solve this problem by shunt‐connecting a motor‐driven mechanical load to the cage wind generator. For driving mechanical loads, the induction motor is most widely used in industries. This paper studies the terminal voltage holding effect of an induction machine during grid voltage sag due to the magnetic flux holding effect and the saturation characteristic. Taking advantage of this effect, the induction motor that is used for driving mechanical load is then proposed to improve the LVRT capability of wind turbine generators. Furthermore, the change of the rotating speed or slip of the induction machine is found to have a great impact on improving the LVRT. By adding some inertia to the motor‐driven mechanical load, an enhanced voltage holding effect, and therefore LVRT improvement, is expected for the wind farm. Both simulation and experimental results prove the effectiveness of the proposed method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Study concerning production of lightning overvoltages on low‐voltage power distribution lines

In order to study lightning problems of low‐voltage power distribution lines, lightning overvoltage waveforms were observed inside the homes of customers. The cause of lightning overvoltages was examined from observation of striking points by still cameras. Lightning overvoltages of 62 waveforms were recorded by observation over a period of about 3 1/2 years. Observed waveforms can be classified into three types of single polarity (positive or negative), both polarities (which change from positive to negative or negative to positive), and pulsive waveform. The causes of these lightning overvoltages which were estimated from striking points are shown as follows: (1) Induced lightning overvoltages on low‐voltage distribution lines. (2)   Electric potential rise due to discharge of surge arresters or current of overhead ground wire. (3)   Shift of lightning overvoltages from high‐voltage side of transformer to low‐voltage side, which is due to electromagnetic induction. © 2000 Scripta Technica, Electr Eng Jpn, 130(4): 66–75, 2000     

Crosstalk‐noise‐aware bus coding with low‐power ground‐gated repeaters

Crosstalk noise is one of the serious reliability concerns in nanoscale integrated circuits. Repeater insertion together with shielding wires is a typical method to suppress crosstalk noise associated with global data bus. A new crosstalk‐noise‐aware bus coding scheme with ground‐gated repeaters is proposed in this paper to minimize the routing overhead as well as power consumption of data bus systems. A subset of 4‐to‐6 crosstalk‐noise‐aware codes is selected to minimize the number of simultaneous data transitions. The routing overhead is reduced by 12.31% with the new bus coding scheme compared with the conventional data bus with shielding wires. Furthermore, the leakage power and worst‐case active power consumptions are reduced by 12.5% and 18.26%, respectively, with the new crosstalk‐noise‐aware data bus system as compared with the previously published bus coding system in an industrial 40‐nm CMOS technology.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.