新型差动输入CMOS电流传送器及其应用

基于P阱CMOS工艺提出了一种新的差动输入电流传送器。通过引入误差抑制负反馈电路,有效地减小了信号失真,拓宽了电路线性动态范围。文中还详细分析了电路性能,并由此指导电路的优化。给出的几个典型应用电路表明,与第二代电流传送器（CCII）相比,差动输入电流传送器的通用性更强,可获得较简洁的电路结构。本文最后设计了一个既可作为电流模式又可作为电压模式的MOSFET－C二阶滤波器。PSPICE模拟表明所提出的电路与其它同类电路相比具有更好的电路特性。     

一种新颖的CMOS差动电压电流传送器及其应用

针对第二代电流传送器（ＣＣⅡ）的不足之处,提出了一种新颖的差动电压输入电流传送器（ＤＶＣＣ）。首先给出了ＤＶＣＣ的ＣＭＯＳ集成工艺实现方法,并分析了其工作原理。然后给出其具体应用实全儿ＰＳＰＩＣＥ的模拟结果,验证了实现和应用ＤＶＣＣ的可行性。     

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13- $muhbox{m}$ standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 $hbox{mm}^{2}$.      

A FG-MOS Based Fully Differential Current Controlled Conveyor and Its Applications

This paper presents a new fully differential second generation current controlled conveyor (FDCCCII) based on differential pair topology, which employs floating gate MOS transistors (FG-MOS). It uses floating gate MOSFETs at the input stage and has rail-to-rail structure which performs with both positive and negative signals. This circuit has tunable parasitic resistance at its input port. It operates with low supply voltage (±0.8 V), low power consumption (lower than 3 mW at current bias of 1 mA), and wide range parasitic resistance (R _X ). This circuit has less MOSFET than the previous similar circuits and is suitable for integrated circuit design. To demonstrate the application of the proposed circuit, a fully differential current mode LC-ladder filter and a fully differential multifunction biquad filter are designed. Simulation results by HSPICE confirm validity of the proposed circuit and its application.     

Bulk-Driven Current Differencing Transconductance Amplifier

Low-voltage (LV) low-power (LP) integrated circuit design is becoming a leading trend in VLSI technology, particularly in special portable applications. In this paper, the principle of a bulk-driven MOS transistor is employed in the design of a novel LV LP current differencing transconductance amplifier (CDTA). Designs in the 0.25 μm CMOS technology have been verified via PSpice simulation. The supply voltages are only ±0.6 V.     

Chopper Modulators Using Current Conveyor Analogue Switches

The new CMOS Cowan, Ring, and Full-AM chopper modulators using current conveyor analogue switches are presented. The proposed chopper modulators use a square wave carrier current for controlling the transfer of a sine wave baseband voltage from nodes Y to nodes X, and the baseband currents from nodes X to nodes Z, of the current conveyors. The proposed chopper modulators are verified by simulating from the layout with a 0.5 μ m/level 49 MOSFET model of AMI obtained through MOSIS. With a supply voltage of ± 1.5 V, the operation range for the baseband voltage is between −300 mV and 300 mV. The operation range for the carrier current, bias currents for CCIIs, is ranged from ten to few hundred microamps. Using the carrier current of 20 μ A, the power consumption is not more than 0.8 mW in the operation range of the baseband voltage.     

Realization of Series and Parallel R-L and C-D Impedances Using Single Differential Voltage Current Conveyor

In this paper, realization of series and parallel R-L immitances using differential voltage current conveyor (DVCC) is presented. The proposed circuits enable actively simulation series and parallel R-L and (-R)-(-L) immitances. Applying RC:CR transformation to the proposed configurations, series and parallel C-D and (-C)-(-D) simulators can also be realized with the same topology. They employ single DVCC and at most three resistors and one capacitor. No component matching constraints are imposed for the realisations. The performance of the proposed immittance simulators is demonstrated on both a second-order voltage and second-order current-mode filters. PSPICE simulations are given to verify the theoretical analysis. An erratum to this article is available at .     

基于PLC的PSO算法PID输送机速度控制技术研究

本文主要利用粒子群优化算法(PSO)确定输送机系统速度控制中的最佳PID控制器增益。该项目通过三菱Q系列UDV PLC实现,该PLC带有多个编码器传感器和一个内置以太网模块来监控反馈。为了验证该方法的性能,将PSO离线确定的最优增益应用于模拟器和实际模型。实验结果表明,与其它方法相比,所提出的基于粒子群算法的PID控制...     

Novel All-Pass Filter Section Using Differential Difference Amplifier

A novel high-performance first-order all-pass filter employing a single active element and a minimum number of passive components is presented. The proposed circuit is based on differential difference amplifier and is very suitable for low voltage operation. Also, the use of grounded capacitor enables its implementation with standard CMOS technologies. SPICE simulation and experimental results verifying theoretical analyses are also provided.     

Maintainability Applications Using the Matrix FMEA Technique

The Matrix Method of Failure Modes and Effects Analysis (FMEA) provides an organized and traceable analysis from the piece-part failure-mode through all indenture levels to system-level failure effects. This paper describes a methodology for reversing the buildup process for maintainability analysis. The output of this reverse process identifies each system-failure effect individually and the related indentured, lower-level composition of contributing sources of failure. The results of this technique provide source data for identifying different levels of ambiguity for fault isolation, evaluating test point adequacy, formulating replacement level criteria, developing maintenance diagnostic charts and procedures, validating maintenance concepts, and segregating most-probable faults for spare parts requirements.     

New Compact CMOS Li-Ion Battery Charger Using Charge-Pump Technique for Portable Applications

This paper presents a new compact CMOS Li-Ion battery charger for portable applications that uses a charge-pump technique. The proposed charger features a small chip size and a simple circuit structure. Additionally, it provides basic functions with voltage/current detection, end-of-charge detection, and charging speed control. The charger operates in dual-mode and is supported in the trickle/large constant-current mode to constant-voltage mode with different charging rates. This charger is implemented using a TSMC 0.35-mum CMOS process with a 5-V power supply. The output voltage is almost 4.2 V, and the maximum charging current reaches 700 mA. It has 67.89% power efficiency, 837-mW chip power dissipation, and only 1.455times1.348 mm² in chip area including pads     

宽范围 CMOS差分式双端输入-输出电流传输器

基于宽线性跨导及共模检测电路,设计了一种改进型差分式双端输入-输出电流控制电流传输器电路(DIDOCC)。该全差分式电路具有电流控制功能,并能抑制偶次谐波和共模干扰。仿真结果表明,在-1.5～+1.5V供电电压下,总静态电流约为300μA,X1、X2端差分电压输入动态范围为-0.9～0.9V。基于DIDOCC电路,设计了一种全差分二阶滤波器,仿真结果与理论值较为吻合。文中所有电路均基于0.25μmCMOS工艺。     

True Broadband Technique for On-Chip-Series Connection of TWAs Using Differential Distributed Amplifiers

A new technique for series connection of monolithic broadband travelling wave amplifiers (TWAs) is presented, using differential distributed architectures. This technique is intrinsically broadband because no series capacitor is used, it starts operating at dc up to cut-off frequency. With a GaAs heterojunction bipolar transistor monolithic microwave integrated circuit process, two on-chip-series coupled 18 dB gain and 23 GHz cut-off frequency TWAs are realized. Our approach avoids packaging steps and hybrid components. This is a very promising result for monolithic high-gain broadband amplifiers.     

逐次逼近型(SAR)模数转换器在马达控制中的应用

引言 在一个典型的马达控制系统中(图1),马达相位线圈的电流和电压经由微控制器(μC)或DSP来测量和转换成数字信号.由于有高电压在马达相位线圈上,隔离的霍尔效应闭环传感器将马达的场信号转换成在A/D的输入范围内的电压信号.多通道SAR(逐次逼近)A/D转换器被用来做同步取样以得到正确相位信号.本文将分析闭环电流传感器及如何从A/D转换器实现最佳的信燥比.在此,我们采用ADS7864(6通道、12位、500KSPS)逐次逼近型A/D转换器.     

基于对称差分算法的背景更新和运动检测

本文针对时间差分将导致差分图像中背景显露过多影响了背景模型建立的缺点,利用对称差分能够快速检测中间帧运动目标的特点,提出一种使用间隔多帧对称差分来更新背景模型,从而建立可靠的背景模板,再结合背景消减进行运动检测的方法。实验表明该算法能快速地建立背景模型,同时有效地检测出背景中的运动物体,具有一定的实际应用价值。     

基于电流折叠技术的CMOS全差分VCO设计

针对目前通信系统应用上对压控振荡器的片上集成、宽调谐、调幅、启动特性和功耗等提出的综合性要求,分析和设计了一种压控调频调幅振荡器,其延迟单元采用全差分结构,以消除共模噪声和增加延迟控制的灵活性;并利用交叉耦合的差分负阻和电流折叠的正反馈技术进行频率调谐,使之在宽频范围内具有常数振荡幅度.采用0.5 μm CMOS工艺进行spice仿真,结果表明振荡器具有34～197 MHz的宽调谐范围,并能保持常数振荡幅度,功耗仅10mw,启动时间仅52 ns.系统还能在0.5～2.0 V范围内进行良好的线性调幅.     

CMOS Active Inductor Linearity Improvement Using Feed-Forward Current Source Technique

MOSFET drain current second-order nonlinearity has a significant impact on the linearity of current regulated CMOS active inductors. It tends to compress MOSFET transconductance $(g_{m})$ by generating excess dc current $(I_{rm EX})$ in the channel, which is a function of incoming input signal amplitude. This generated excess dc current can change the original dc operating point of the current regulated CMOS active inductor, and thus, influence the inductance. Unfortunately, MOSFET drain current second-order nonlinearity contributes more to MOSFET $g_{m}$ compression than MOSFET drain current third-order nonlinearity. In this paper, a new technique known as feed-forward current source (FFCS) has been proposed to improve the linearity of the active inductor. The proposed FFCS technique makes use of the second-order nonlinear property of a MOSFET that generates $I_{rm EX}$ when an input ac signal is applied. The generated $I_{rm EX}$ is then fed-forward to the current source of the active inductor to drain out the $I_{rm EX}$ in the active inductor. This prevents the dc operating point from shifting and improves its inductance linearity. Single-ended and differential active inductors with the proposed FFCS circuit have been fabricated using Silterra's CMOS 0.18-$mu{hbox{m}}$ technology to verify the proposed technique.      

通信应用中差分电路设计的相关技术

以足够的保真度成功捕获信号是通信系统设计的一大难题。严格的标准规范会要求选择合适的接口拓扑结构。本期座谈介绍了差分设计技术的优势,以及其性能优势在当今高性能通信系统中如何影响严格的系统需求。此外,将回顾射频的定义,概要说明系统预算,并对比不同的实现方法。     

A Microfluidic Packaging Technique for Lab-on-Chip Applications

In this paper, we address the often-neglected challenges of microfluidic packaging for biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. This low-cost procedure is performed through a programmable dispensing system right after a routine electronic packaging process. In order to prove the concept, the simulation, fabrication and chemical testing results of implemented hybrid system incorporating microelectronics and microfluidics are also presented and discussed.