An Output Buffer for 3.3-V Applications in a 0.13-μm 1/2.5-V CMOS Process

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mum CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13-mum 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly     

High-voltage-tolerant I/O buffers with low-voltage CMOS process

This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-μm process with 40-Å gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor     

A 3.3-V/5-V low power TTL-to-CMOS input buffer

A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applications. It has low power dissipation, high operating speed, and a logic threshold voltage less sensitive to process and supply voltage variations. The proposed SSIB input buffer was realized in a 0.8-μm single-polysilicon double-metal (SPDM) CMOS technology, The measured logic threshold voltage variations due to process variations are ±24 mV for 5 V supply and ±16 mV for 3.3 V supply, respectively. Its logic threshold voltage variations due to supply voltage variation from 3.3 V to 5 V are within 10 mV. In ring oscillator configuration, the measured delay and power dissipation are 0.45 ns and 0.37 mW for 5-V supply and 0.51 ns and 0.14 mW for 3.3-V supply, respectively     

Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology

A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3Vinterface.Anew level converter realized with +1.8Vdevices that can convert 0/1Vvoltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.     

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-$mu$m CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18-$mu$m (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.     

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal–insulator–metal (MIM) capacitors with $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ stacked dielectrics for precision analog circuit applications. By using the “canceling effect” of the positive quadratic voltage coefficient of capacitance (VCC) of $hbox{Sm}_{2}hbox{O}_{3}$ and the negative quadratic VCC of $hbox{SiO}_{2}$, MIM capacitors with capacitance density exceeding 7.3 $hbox{fF}/muhbox{m}^{2}$ , quadratic VCC of around $-hbox{50} hbox{ppm/V}^{2}$ , and leakage current density of $hbox{1} times hbox{10}^{-7} hbox{A/cm}^{2}$ at $+$3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.      

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

5 V compatibility with 3.3 V-only CMOS ASICs

A 3.3 V-only CMOS I/O buffer is proposed that interfaces with 5 V CMOS and TTL devices. This new buffer eliminates the 5 V power supply bus on the application specific integrated circuit (ASIC) chip while greatly improving the performance and reliability of the I/O buffer. In addition, the cost of packaging these ASICs is reduced due to removing the need of supporting a 5 V power plane on the package. The interfacing issues and the characteristics of the proposed I/O buffer are examined in detail.     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

$hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition

For electronic applications, we have fabricated VO₂ thin-film variable resistors (varistors) using metal-insulator transition regarded as the abrupt current jump. The increase of the number of parallel stripe patterns in the varistor leads to the increase in current below a current-jump voltage, which endures a high surge voltage with high current and short rising time. Electrostatic discharge (ESD) experiments show that the varistic coefficient of 500 is larger than 30-80, which is known for commercial ZnO varistors. In overvoltage-protection tests applying high ESD voltages up to 3.3 kV to a varistor, the maximum response voltage is lower than 200 V at an ESD voltage of 1600 V, and the electronic response time is less than 20 ns. This is sufficient to protect a device perfectly.     

High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4     

A Temperature Sensor With an Inaccuracy of ${-}{hbox{1}}/{+}{hbox{0.8}} ^{circ}$ C Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits

This paper proposes an accurate four-transistor temperature sensor designed, and developed, for thermal testing and monitoring circuits in deep submicron technologies. A previous three-transistor temperature sensor, which utilizes the temperature characteristic of the threshold voltage, shows highly linear characteristics at a power supply voltage of 1.8 V or more; however, the supply voltage is reduced to 1 V in a 90-nm CMOS process. Since the temperature coefficient of the operating point's current at a 1-V supply voltage is steeper than the coefficient at a 1.8-V supply voltage, the operating point's current at high temperature becomes quite small and the output voltage goes into the subthreshold region or the cutoff region. Therefore, the operating condition of the conventional temperature sensor cannot be satisfied at 1-V supply and this causes degradation of linearity. To improve linearity at a 1-V supply voltage, one transistor is added to the conventional sensor. This additional transistor, which works in the saturation region, changes the temperature coefficient gradient of the operating point's current and moves the operating points at each temperature to appropriate positions within the targeted temperature range.      

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm,3.5-nm Tox, 1.8-V CMOS technology

This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation     

An α-immune, 2-V supply voltage SRAM using a polysilicon PMOSload cell

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured     

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications.     

Fabrication and Properties of $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85} hbox{Ti}_{3}hbox{O}_{12}/breakhbox{HfO}_{2}/hbox{Si}$ Structure for Ferroelectric DRAM (FEDRAM) FET

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with 400-nm-thick $hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}$ (BNdT) ferroelectric film and 4-nm-thick hafnium oxide $(hbox{HfO}_{2})$ layer on silicon substrate have been fabricated and characterized. It is demonstrated that the $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ structure exhibits a large memory window of around 1.12 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 10% degradation in the memory window after $hbox{10}^{10}$ switching cycles. The retention time is 100 s, which is enough for ferroelectric DRAM field-effect-transistor application. The excellent performance is attributed to the formation of well-crystallized BNdT perovskite thin film on top of the $ hbox{HfO}_{2}$ buffer layer, which serves as a good seed layer for BNdT crystallization, making the proposed $hbox{Pt}/hbox{Bi}_{3.15}hbox{Nd}_{0.85}hbox{Ti}_{3}hbox{O}_{12}/ hbox{HfO}_{2}/hbox{Si}$ suitable for high-performance ferroelectric memories.      

Performance Improvement of $hbox{Sm}_{2}hbox{O}_{3}$ MIM Capacitors by Using Plasma Treatment After Dielectric Formation

In this letter, we investigate the dependence of the performance of metal-insulator-metal (MIM) capacitors with Sm₂O₃ dielectric on plasma treatment (PT) performed before Sm₂O₃ deposition, after Sm₂O₃ deposition, or both before and after Sm₂O₃ deposition. By performing PT in N₂ ambient (PTN) after Sm₂O₃ dielectric formation, the effective quadratic voltage coefficient of capacitance (VCC) can be reduced from 498 to 234 ppm/V² and the effective linear VCC can be reduced from 742.3 to 172 ppm/V for MIM capacitor with Sm₂O₃ dielectric having a capacitance density of ~ 7.5 fF/mum². The leakage current density at +3.3 V can be reduced from 3.44 10^-7 to 1.60 times 10^-8 A/cm² by performing PTN in both before and after Sm₂O₃ deposition. PTN after dielectric formation is an effective way to improve the performance of high-kappa dielectric MIM capacitors for RF and analog/mixed signal IC applications.