Study of Electron Mobility in 4H-SiC Buried-Channel MOSFETs

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

4H-SiC隐埋沟道MOSFET迁移率的研究

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

Influence of mobility model on extraction of stress dependent source–drain series resistance

The extraction of the parasitic source–drain series resistance after stress is a significant challenge, which has not been reported for channel lengths below 0.5 μm. Methods proposed until now yield a reducing series resistance behaviour for such channel lengths, contrary to expectation. We demonstrate that the underlying cause of this phenomenon is due to modification of mobility behaviour under stress. A new methodology for monitoring the time dependent progression of series resistance and mobility degradation for stress conditions varying from hot carriers to Negative Bias Temperature is proposed. A new threshold voltage model separating the effects of damaged and undamaged portions of a stressed device is also demonstrated.     

An accurate semi-empirical saturation drain current model for LDDn-MOSFET

Based on a new empirical mobility model which is solely dependent on V_gs, V_t and T_ox, a corresponding semiempirical I_dsat model for n-MOSFET including velocity saturation, mobility degradation due to increased vertical effective field, and source/drain series resistance of LDD structures is reported in this paper. A good agreement among the model and the measurement data from several different technologies is shown. Prediction of I_dsat for the future generations of device scaling and low-power applications by using this new model is presented     

A total resistance slope-based effective channel mobilityextraction method for deep submicrometer CMOS technology

A simple yet effective total resistance slope-based method for extracting the effective channel mobility in deep submicrometer CMOS technology is developed. Using the slope of the measured total resistance versus mask length, the series resistance is removed from the measured total resistance, and mobility is extracted without involving the effective channel length. The new method facilitates mobility extraction in situations where the effective channel length is difficult to extract, such as in lightly-doped-drain (LDD) devices or at low temperatures. The new method also allows the series resistance to be any function of the gate bias, making the mobility extraction in LDD devices easier and more accurate     

Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices

In this work, we investigate the gate voltage and the geometry dependence of the series resistance and the carrier mobility in n-type and p-type FinFETs. A significant gate voltage dependence of the series resistance is observed, which is ascribed to the conduction modulation of the LDD region under the gate. The fin width dependence of the series resistance is investigated and two simple methods of normalization are compared. Mobility data in narrow (W_fin = 30 nm) and wide fin (W_fin = 3μm) have been compared. N-FinFETs show a higher mobility compared to the p-FinFET in both cases, but for narrow fins the difference is reduced since the mobility on the sidewalls improves for holes but degrades for electrons. We show that without taking into account the gate voltage dependence of the series resistance the mobility is significantly underestimated.     

Extraction method for source series resistance and transverse field mobility reduction coefficient using the MOSFET saturation region

A new extraction method for source series resistance and mobility reduction coefficient with transverse field, based on the MOSFET transconductance modeling in the saturation region, is reported. The simple associated transconductance model also appears to be extremely useful for optimal parameter extraction. The proposed method is validated on partially depleted SIMOX MOSFETs.     

Basic parameter measurement and channel broadening effect in the submicrometer MOSFET

An improved measurement technique of the basic MOSFET parameters is presented. This method is based on the measured data of two identical devices with different channel lengths. The effect of series resistance and channel length can be separated from the mobility measurement. This is the only method in which it has been proved that mobility can be measured on a short channel device. A new technique of channel length and series resistance is done by the measurement of newly defined quantity, RTK, which is the equivalent channel length that includes the effect of series resistance. Because of the success of this measurement method, a new phenomena, which we call channel broadening effect, was investigated. Its effects on the submicrometer device characteristics were investigated.     

Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance

The electron mobility behaviour in submicron MOSFETs is studied in the temperature range of 77–300 K. As the effective channel length is reduced, the effective mobility as well as the field-effect mobility are found to decrease and to become less temperature dependent. These experimental results are explained by the influence of series resistance and effective channel length, which are both temperature dependent. The possibility of accurate determination of series resistance and “pure” mobility is demonstrated. A new method is proposed to determine submicron MOSFET channel length at low temperatures.     

Extraction of series-resistance-independent MOS transistor modelparameters

It is shown by simulations and experiments how series-resistance-independent intrinsic SPICE level-3 MOS parameters can be extracted when the source and drain series resistance is extracted as a separate parameter. If this resistance is not extracted separately, not only will the mobility reduction factor depend on the series resistance but so will the maximum drift velocity, the saturation field factor, and the static feedback factor. External source and drain resistors have been used to investigate how these parameters depend on the series resistance     

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.     

A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors

This paper reports the early stage of dc hot carrier degradation behaviour of n-channel low doped drain metal oxide semiconductor field effect transistors in a range of deep sub-micron technologies. A deviation from the normally observed power-law expression tⁿ at short time scales is revealed. In addition, under V_G=V_D condition, anomalous behaviour characterised by a saturation in the transconductance degradation prior to the power-law regime is observed. The factors contributing to the damage evolution are analysed by extraction of the parasitic source–drain series resistance and the effective mobility. Depending on the voltage rating of the technology, the relative contributions of these two underlying causes, at various times, to the total degradation are different. For the 5 V technologies, both the series resistance and the mobility play significant roles, with the early stage dominated by an increase in series resistance. On the other hand, the series resistance has a negligible influence relative to the mobility on the degradation mechanism of the 3 V technologies.     

Characterization for High-Performance CMOS Using In-Wafer Advanced Kelvin-Contact Device Structure

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current–voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method.      

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

Predicting CMOS speed with gate oxide and voltage scaling andinterconnect loading effects

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I_dsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted     

Circuit Model Simulation of Gunn Effect Devices

A circuit model of the Gunn device that retains both the time dependent and nonlinear device properties is presented. The model is based on the physical properties of a high-field domain in a uniformly doped sample and represents this domain and the remainder of the device by appropriate circuit elements. A computer program has been written that allows the device to be connected to any combination of RLC elements up to and including two parallel RLC circuits in series. Computer calculations have been made with a low resistance series circuit to simulate the Gunn mode of operation. The variation of Gunn frequency with bias voltage has been calculated and is in qualitative agreement with experiments. An inductance of 1 nH in series with 1 ohm is found to significantly alter results in comparison with the pure resistive case. The effect of this series inductance has also been observed experimentally as a lack of harmonics in resistive device mounts with stray inductance. Results obtained with a parallel RLC circuit point out the importance of circuit voltage control on the domain behavior. The LSA diode is treated as a bulk conductance following the drift velocity-electric field curve for GaAs. The bulk velocity and differential mobility are approximated by polynomials of electric field from which the device equivalent circuit is obtained. A physical insight into the operation of the LSA device is gained through a plot of time-integrated differential mobility with time. It is shown that an RF load for which this integral does not change appreciably over an RF period results in maximum efficiency. Results of efficiency and negative resistance of the device obtained for a bias field of 10 kV/cm are presented and are in good agreement with calculations of other workers.     

Charge extraction by a linearly increasing voltage of photo-generated carriers: The influence of two mobile carrier types,bimolecular recombination,and series resistance

The charge extraction by a linearly increasing voltage (CELIV) technique is a well-known and commonly used method to characterize charge transport in low-mobility materials. In the original CELIV theory it is assumed that one type of charge carrier is mobile and the other fixed and that recombination during the extraction pulse is negligible. However, this is in general not the case, especially in photo-CELIV where both electrons and holes are generated by light excitation. Moreover, RC effects induced by the series or load resistance of the external circuit are typically assumed to be negligible. In this work, we use drift-diffusion modelling and analytical derivations to show that the standard equations used for calculating the mobility in the moderate conductivity regimes generally leads to errors in the mobility determination in the case when i) two carrier types of similar mobility, ii) recombination, iii) an electric-field-dependent mobility, and iv) RC effects are present in the device. The effect of the external series resistance on the mobility determination becomes of particular importance in devices with relatively large mobilities and/or high carrier concentrations, where the original CELIV theory might give rise to an underestimation of the mobility by several orders of magnitude.     

Effects of Mechanical Strain on Characteristics of Polycrystalline Silicon Thin-Film Transistors Fabricated on Stainless Steel Foil

The effects of uniaxial tensile strain on the performance of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported. Longitudinal strain increases the electron mobility and decreases the hole mobility, while transverse strain decreases the electron mobility and slightly decreases the hole mobility. Under longitudinal strain the off current decreases for both NMOS and PMOS TFTs and shifts in threshold voltage and substhreshold slope are observed for p-channel TFTs. A strong dependence on channel length for both electron and hole mobilities under longitudinal strain indicates the presence of a series resistance. For poly-Si TFTs, the mobility changes under strains are related to the strain effects on single crystalline silicon devices.      

A review of DC extraction methods for MOSFET series resistance and mobility degradation model parameters

The performance of modern MOSFETs is limited by the presence of parasitic series resistances and mobility degradation. This article reviews and assesses 18 of the extraction methods currently used to determine the values of parasitic series resistances and mobility degradation from the measured drain current. The methods are separated in 3 groups: seven different methods that use the transfer characteristics of several devices having different mask channel lengths; five methods based on a single device with different drain and gate bias; six methods which account for the asymmetry between drain and source resistance.