Wide-band transimpedance amplifiers using AlGaAs/InxGa1-xAs pseudomorphic 2-DEG FET's

Monolithic wide-band amplifiers have been demonstrated using AlGaAs/In_xGa_1-xAs/GaAs pseudomorphic two-dimensional electron-gas field-effect transistors. The amplifiers have yielded an 18.0 GHz bandwidth and a 41.8 dBΩ transimpedance gain with a feedback resistance of 100 Ω. In addition, the dependence of In mole fraction for an In_xGa_1-xAs channel layer on device and amplifier performance has been also investigated. The g_m and the f_T in a device, along with the bandwidth, the gain, and the noise performance in an amplifier, have improved as the In mole fraction is varied from 0 to 0.25     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

100-Gb/s Packet Signal Generation With Spectral Efficiency Larger Than 1 bit/Hz/s

We have experimentally demonstrated how to generate 100-Gb/s packet signals with spectral efficiency higher than 1bit/Hz/s for the first time. The optical packet with 3.125-Gb/s label and 100-Gb/s return-to-zero differential quadrature phase-shift-keying payload are generated by using optical carrier-suppression and separation and vestigial sideband filtering techniques. The performance of transmission and label erasure has also been evaluated.     

The origination and optimization of Si/SiO/sub 2/ interface roughness and its effect on CMOS performance

As CMOS device dimensions scale down to 100 nm and beyond, the interface roughness between Si and SiO/sub 2/ has become critical to device performance and reliability. Si/SiO/sub 2/ interface roughness degrades channel mobility decreasing drive currents. The authors have used atomic force microscopy to study surface roughness in the processing of 0.16 /spl mu/m CMOS integrated circuits. All of the process steps that could potentially affect the interface roughness have been studied. The results show that oxidation is the major contributor to the interface roughness. The rms roughness is found to be linearly dependent on oxide thickness. Transistors with Si/SiO/sub 2/ interface rms roughness that has been reduced from 1.6 to 1.1 /spl Aring/ by reducing oxide thicknesses show improved device drive currents. This technique for interfacial smoothing and device performance improvement has the advantage of being easily implemented in today's technology.     

Blanket SMT With In Situ N2 Plasma Treatment on the $langle hbox{100} rangle$ Wafer for the Low-Cost Low-Power Technology Application

PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with $langle hbox{100} rangle$ orientation has been observed, and the degradation mechanism is examined. The boron-doping loss from both the PMOS gate and the source/drain region during the SMT process is the root cause. In situ N2 plasma treatment before the SMT layer deposition has been implemented for the first time to recover PMOS performance on the $langle hbox{100} rangle$ wafer by reducing the boron-doping loss from the gate and the source/drain region. Reliability like PMOS NBTI has been examined, and no degradation is observed.      

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO/sub 2/ gate dielectrics

Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.     

A Single-Ended Resistive $X$-Band AlGaN/GaN HEMT MMIC Mixer

A broadband highly linear X-band mixer in AlGaN/GaN monolithic microwave integrated circuit technology has been designed, processed, and characterized. The design is based on a 4 times 100 mum AlGaN/GaN HEMT in a single-ended circuit topology. The mixer has an IF bandwidth of 2 GHz with a conversion loss (CL) of < 8 dB across the X-band with a minimum CL of 6.9 dB at 11 GHz. The large-signal performance is exemplified by IIP 3 levels of 22 and 30 dBm at local oscillator drive levels of 15 and 23 dBm, respectively. A minimum noise figure of 9 dB is achieved at 11.6 GHz.     

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time, 900 mW power dissipation, and a chip size of 18.3 mm/SUP 2/ has been developed for caches and control memories of high-performance computer systems. The 1K/spl times/4 organisation mode combines the lower cost per bit of a 4K-bit device with the higher memory-module design flexibility of a 1K word unit. The excellent speed performance together with the high packing density have been achieved by using an oxide isolation technology with oxide-walled emitters in conjunction with novel circuit techniques.     

GaAs MESFET laser-driver IC for 1.7-Gbit/s lightwave transmitter

GaAs monolithic integrated circuits for modulating junction lasers (laser drivers) have been developed for a 1.7-Gb/s lightwave communication system. The modulation currents can be varied continuously from a few mA up to 50 or 100 mA, depending on the types of laser drivers. It has been demonstrated that devices of the low-current type are capable of driving a 50-Ω load with a 50-mA modulation current with pulse rise and fall times (10% to 90%) less than 200 ps, and the high-current devices are capable of driving a 25-Ω load with up to 100-mA modulation current with pulse rise and fall times less than 250 ps. Nearly temperature-independent performance has been achieved from 0°C to 70°C. The laser drivers are also capable of providing output DC currents proportional to the duty cycle of input data for the purpose of duty-cycle-independent feedback control of junction lasers. The circuit designs and performance of these devices are described     

100Gbit/s 光波分复用系统商用的进一步考虑

Along with the emergence and maturity of 100Gbit/s technologies, numbers of trial and commercial 100Gbit/s Wavelength Division Multiplexing (WDM) systems have been established worldwide. The research- oriented lab tests of 100Gbit/s WDM systems were done by China Unicom in 2012. The 100Gbit/s technologies of polarization multi-plex-quadrature phase shift keying with co-herent detection from multiple vendors have been studied. There are some further issues to be specified before the commercial application of 100Gbit/s WDM system is implemented in large scale in backbone network, including optical performance parameters, optical performance monitoring of 100Gbit/s system, protection mechanism, selection of client interface and comprehensive Operation, Administration and Maintenance (OAM).     

100Base-T/IEEE 802.12/packet switching

Three LAN technologies look set to satisfy the ever-increasing demand for LAN bandwidth. Two of these technologies are 100 Mb/s shared-medium LANs: 100Base-T (aka IEEE 802.3 Fast Ethernet) and IEEE 802.12 (aka 100VG-AnyLAN or 100VG). The third technology is packet switching, which is really an extension of existing LAN bridge technology, but offers excellent performance gains at very low cost. The authors describe the three technologies and provide a comparison between the two 100 Mb/s LANs. Also presented are results that compare the measured performance of 100 Mb/s shared-medium LANs with switched LANs     

Ga0.47In0.53As depletion mode MISFETs withnegligible drain current drift

Ga_0.47In_0.53As depletion-mode metal insulator semiconductor field-effect transistors with a transconductance in the range 100-140 mS/mm and with no significant current drift (less than 3% in 30 hours) have been fabricated on epitaxial layers grown by MOCVD. This high performance has been achieved using an efficient passivation of the GaInAs surface which associates in situ native oxide removal by a hydrogen multipolar plasma and a Si₃N₄ film deposition     

Fabrication and performance of GaAs p+n junction and Schottky barrier millimeter IMPATT's

A recently developed procedure, incorporating both preferential electrochemical etching for wafer thinning and electroplating for heat sink formation has been applied to the fabrication of Kaband (26.5-40 GHz) GaAs IMPATT's. Both epitaxially grown GaAs p⁺n junction and Cr Schottky barrier diodes have been fabricated. This procedure makes possible the batch fabrication of small area diodes (<2 times 10^{-5}cm²) over a large wafer area. The diodes have been operated both in the oscillator and stable-amplifier mode. Power, efficiency, and noise performance of the devices is reported. The p⁺n diodes, which could withstand junction temperature of over 300°C, gave the best power and efficiency. Powers as high as 680 mW with 12.4 percent efficiency at 34.8 GHz and an efficiency as high as 16 percent with 390 mW at 29.5 GHz have been achieved. The Cr Schottky diodes were unable to withstand junction temperatures in excess of 200°C and therefore produced less power despite the potentially better power handling capability. The highest power obtained from a Cr Schottky is 470 mW with 12.5 percent efficiency at 34 GHz. Comparable oscillator noise performance has been obtained with both types of diode. The best AM (DSB) double sideband NSR obtained is -135 dB in a 100 Hz window at 1.5 MHz from the carrier. An rms frequency deviation as low as 13 Hz in a 100 Hz window has been observed with a power output of 164 mW at 35.4 GHz by raising the external Q to 138. A lowest FM noise measure of 23 dB was achieved by reducing output power to 16 mW. The amplifier noise figure measured for both p⁺n and Cr Schottky diodes is 26 dB.     

A 6-Bit/200-MHz Full Nyquist A/D Converter

This paper deals with the development of an extremely fast 6-bit flash A/D converter. To gain insight into the nature of speed limitations, the effects arising from operation at very high sampling rates have been investigated. This led to the implementation of an optimized double-stage comparator circuit. The chip has been fabricated in a fast standard oxide isolated bipolar process. At a sampling rate of 200 MHz, measurements show excellent dynamic performance (high signal-to-noise ratio, no error codes) up to input frequencies of 100 MHz.     

Modified PEDOT-PSS Conducting Polymer as S/D Electrodes for Device Performance Enhancement of P3HT TFTs

Poly(3,4-ethylenedioxythiophene)—Polystyrene Sulfonate (PEDOT-PSS) is the most widely used conducting polymer as electrode material in organic (polymer) devices. However, commercially available PEDOT-PSS in our experiment has a relatively low conductivity that reduces the device performance when it is used for electrode material. The purchased PEDOT-PSS has been mixed with polar solvent dimethyl sulfoxide, which increases its conductivity from 0.07 to 30 S/cm. The enhanced conductivity has long-term stability at room temperature and short-term stability at high temperature (100$^circ$C) in air ambient. The modified PEDOT-PSS has been inkjet printed and used as source/drain (S/D) electrodes for poly(3-hexylthiophene) (P3HT) thin-film transistors (TFTs). Unmodified PEDOT-PSS and gold have also been used as S/D electrodes for comparison. The TFTs with modified PEDOT-PSS electrodes show significantly improved performance over the devices with unmodified PEDOT-PSS electrodes and are similar to the devices with gold electrodes. The difference in device performance mainly results from parasitic series resistance. In the devices with unmodified PEDOTT-PSS, high electrode series resistance has several effects on devices, e.g., restricted current growth at high negative gate voltage, reduced on/off current ratio and current output capability.     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

Studies on an In0.53Ga0.47As/In0.52Al0.48As single-quantum-well quasi-MISFET

We describe here the properties of a novel InGaAs/ InAlAs quasi-MISFET in which an inverted modulation-doped single quantum well forms the channel and an undoped semi-insulating InAlAs constitutes the gate barrier. The entire structure is grown lattice-matched to InP continuously by molecular-beam epitaxy in a single step. Rapid thermal annealing of implanted semiconductors and ohmic contacts have been investigated and have been used successfully in the fabrication of the MISFET's. Improved performance is obtained with the incorporation of Ti in the source-drain metallization, with which contact resistances as low as 0.1 ω . mm are measured. Charge-control modeling of the proposed device predicts the carrier concentration in the channel region fairly well at room temperature. A quantum mechanical modeling of the device in the effective mass approximation also has been done. The thickness of the InAlAs doping layer is found to be an important parameter that controls the device turn-on characteristics. The velocity-field characteristics of the two-dimensional channel electrons were measured by pulse current-voltage and pulsed Hall techniques. The maximum velocities measured at 300 and 77 K are 1.5 × 10⁷and 1.7 × 10⁷cm/s, respectively. Fairly high electron mobilities are measured in single-quantum-well MISFET structures even with well thicknesses as small as 100 Å. The InAlAs gate barrier is effective in reducing the gate leakage current. Gate leakage currents are reduced further with a composite dielectric consisting of oxidized Al and InAlAs. An extrinsic transconductance of 310 mS/mm is measured in a 1.0-µm gate device at 300 K. A value of fT= 32 GHz, measured in a 1.0-µm device, is the best obtained so far with this material system. It is expected that submicrometer gate lengths will lead to even better performance.     

On the performance analysis and design of an integrated front-end PIN/HBT photoreceiver

A detailed study on the performance analysis and optimum design of an integrated front-end PIN/HBT photoreceiver for fiber-optic communication is presented. Receiver circuits with two different transimpedance amplifiers-a single-stage common emitter (CE) amplifier and a three-stage amplifier comprising a CE amplifier and two emitter followers (EFs), are analyzed assuming a standard load of 50 /spl Omega/. A technique to include the transit-time effect of a PIN photodetector on the overall receiver circuit analysis is introduced and discussed. Gain-bandwidth product (GB) and gain-bandwidth-sensitivity measure product (GBS) are obtained as functions of feedback resistance (R/sub F/) and various device parameters. Hence, some optimum designs are suggested using a photodetector of area 100 /spl mu/m/sup 2/ and with a feedback resistance of 500 /spl Omega/. The bandwidth plays a major role in determining the optimum designs for maximum GB and maximum GBS. A bandwidth >8 GHz has been obtained for the photoreceiver even with a single-stage CE amplifier. The optimum design for a receiver with a three-stage amplifier shows a bandwidth of 35 GHz which is suitable for receivers operating well beyond 40 Gb/s; however, in this case, the gain is reduced. The performance of different fixed square-emitter structures are investigated to choose the optimum designs corresponding to different gains. Very low power dissipation has been estimated for the optimized devices. The noise performance of the devices with optimum designs was calculated in terms of the minimum detectable optical power for a fixed bit-error rate of 10/sup -9/. The present design indicates that GB and noise performance can be improved by using an optimum device design.     

Operating conditions of the slotted hollow cathode UV Cu+laser

The performance of the UV Cu+ laser in a slotted hollow cathode has been investigated experimentally. The laser power dependent on discharge current, neon pressure, cathode length, and laser mirror transmission has been measured. The optimum neon pressure was found to be 13 mbar. Single-pass gains about 8 percent . m^-1have been evaluated. The observed changes in the slot shape by sputtering during 100 h of operation are briefly discussed. The experimental results are compared to a recent sputtering theory and reasonable agreement is found. The sputtering theory, the spontaneous intensity measurements, and the evaluated gains are used to calculate the number densities of the5sCu+ levels. Laser power is calculated from single-pass gains and agreement with experimental results is obtained.     

A CCD imager overlaid with a thin-film photodetector of a heterojunction ZnSe-Zn1-xCdxTe

A CCD imager which is composed of an interline transfer type scanner in the imaging area and a thin-film photodetector of a heterojunctjon ZnSe-Zn1-xCdxTe has been developed. The array consists of506^{V} times 404^{H}picture elements. The imaging area is about6.7^{V} times 9.0^{H}mm²in size which corresponds to that of a 2/3-in vidicon. For the device to achieve high performance, necessary conditions between the parameters of the overlaid thin-film photoconductor and the scanner have been analyzed. Blooming phenomenon is deeply related to the sensitivity. The blooming has been suppressed without sacrificing the sensitivity by applying the pulse operation of the heterojunction. As a result, excellent performances such as high sensitivity and large blooming suppression have been realized. The scene illumination if F 1.4 100 1x (S/N ratio is 46 dB for luminance signal) in a single-chip color camera. The blooming control capability is 250 times of the saturation exposure.