高温CMOS数字集成电路的瞬态特性分析

本文分析了高温CMOS倒相器和门电路的瞬态特性,建立了它们的上升时间,下降时间和延迟时间的计算公式。根据本文分析的结果,高温CMOS倒相器和门电路瞬态特性变差的原因是由于MOST阈值电压和载流子迁移率降低,以及MOST漏端pn结反向泄漏电流增大的缘故。本文给出的计算结果能较好地解释实验现象。     

高温CMOS数字集成电路的瞬态特性分析

本文分析了高温ＣＭＯＳ倒相器和门电路的瞬态特性，建立了它们的上升时间，下降时间和延迟时间的计算公式。根据本文分析的结果，高温ＣＭＯＳ倒相器和门电路瞬态特性变差的原因是由于ＭＯＳＴ阈值电压和载流子迁移率降低，以及ＭＯＳＴ漏端ｐｎ结反向泄漏电流增大的缘故。本文给出的计算结果能较好地解释实验现象。     

pn结泄漏电流对高温集成MOSFET交流性能的影响

分析了漏源pn结泄漏电流对高温MOS模拟集成电路中、工作在零温度系数(ZTC点)的MOSFET交流参数的影响。研究结果表明,pn结扩散电流对高温MOSFET的交流性能有极大的影响,而产生电流的影响则可以忽略不计。减小泄漏电流对高温MOSFET交流性能影响的重要方法是增加衬底掺杂浓度。还给出了漏源pn结泄漏电流和工作在ZTC点的漏源电流最大允许比例的计算公式。     

高温SO I CMO S 倒相器瞬态特性的研究

本文主要研究高温SOI CMOS倒相器在（27－300℃）宽温区的瞬态特性。研究结果表明：当采用N^ PN^ 和P^＋PP^ 结构薄膜SOI MOSFET组合，并且其结构参数满足高温应用的要求，则SOI CMOS倒相器实验样品在（27－300℃）具有良好的高温瞬态特性。     

宽温区高温体硅CMOS倒相器的优化设计

在对体硅 CMOS倒相器直流特性、瞬态特性的高温模型和高温特性深入研究的基础上 ,提出了高温体硅 CMOS倒相器结构参数设计的考虑 ,给出了宽温区 (2 7～ 2 5 0℃ )体硅 CMOS倒相器优化设计的结果。模拟验证表明 ,所设计的体硅 CMOS倒相器在宽温区能满足下列电学参数设计指标 :输出高电平 Vo H>4 .95 V,输出低电平 Vo L<0 .0 5 V,转换电平 V*i (2 7℃ ) =2 .5 V,V*i(2 5 0℃ ) =2 .4 V,上升时间 tr(2 7℃ ) <110 ns,tr(2 5 0℃ ) <180 ns,下降时间 tf(2 7℃ ) <110 ns,tf(2 5 0℃ ) <16 0 ns。     

高温SOICMOS倒相器MOSFET组合的研究

在讨论薄膜 SOIMOSFET高温性能和高温应用优越性的基础上 ,以高温应用为目标 ,对适用于高温 SOICMOS倒相器的三种 MOSFET组合结构进行了比较分析 ,最终确定了高温 SOICMOS倒相器的 MOSFET组合结构的选取原则。     

CMOS数字集成电路的高温电学性能分析

本文给出了ＣＭＯＳ倒相器的高温等效电路，分析了它的高温直流传输特性和瞬态特性，文章还讨论了ＣＭＯＳ静态数字集成电路高温电学特性的分析方法。本文提出了的ＣＭＯＳ数字集成电路的高温学特性模型和实验结果相接近。     

HEMT DCFL倒相器的模拟分析

本文对HEMT DCFL倒相器直流传输特性及瞬态特性进行了模拟分析.在HEMT单管特性分析中,利用了K.Park的I-V特性分析模型,通过对E/D倒相器的驱动管与负载管工作区域的划分,讨论了电压传输过程中三个不同的工作区;模拟瞬态特性时,分别考虑了电流充放电过程中驱动管和负载管的不同工作状态,较为正确地算出了延迟时间;模拟结果与实验及理论分析吻合.     

高压LDMOS导通电阻的高温特性分析

本文提出了高压LDMOS的高温等效电路,讨论了LDMOS泄漏电流及本征参数在25℃~300℃范围内随温度变化规律.根据本文分析:源漏pn结的反向泄漏电流决定了LDMOS的高温极限温度;导通电阻与温度的关系是(T/T₁)^y(y为1.5~2.5).     

1μm栅HEMT DCFL门电路及环形振荡器的设计与实验研究

利用作者提出的HEMT DCFL倒相器直流传输特性及瞬态特性计算机分析的模型,设计并制成了HEMT DCFL门电路及环形振荡器.在电路设计中,重点讨论了E/D NEMT倒相器的电路性能与器件的主要参数(栅长、栅宽、阈压)间的理论关系.工艺研究中,建立了挖栅时沟道饱和电流Is′与阈压值V_(t~h)间关系的理论曲线,并改进了传统化学湿法刻蚀工艺的阈压均匀性及E,D器件电流匹配的控制精度.实验制作了栅长为1μm的增强型和耗尽型HEMT.在1×1mm范围内,阈压偏差小于50mV,E/D倒相器的传输特性为:V_(OH)≈V_(DD),V_(OL)<0.1V,高、低电平转换范围仅0.1V,噪容达0.3V左右.研制的9级、17级环形振荡器,在V_(DD)为0.5V到3.5V范围内都观察到正弦波振荡波形.     

TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.     

Evaluation of a copper metallization process and the electricalcharacteristics of copper-interconnected quarter-micron CMOS

Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10¹¹ atoms/cm² by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550°C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved     

WSi_2栅和Si栅CMOS／BESOI的高温特性分析

用厚膜ＢＥＳＯＩ（ＢｏｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎ－Ｏｎ－Ｉｎｓｕｌａｔｏｒ）制备了ＷＳｉ２栅和Ｓｉ栅４００７ＣＭＯＳ电路，在室温～２００℃的不同温度下测量了其Ｐ沟、Ｎ沟ＭＯＳＦＥＴ的亚阈特性曲线，分析了阈值电压和泄漏电流随温度的变化关系。     

Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress

We study the degradation of CMOS inverters under DC and pulsed stress conditions before the occurrence of the gate oxide breakdown. Our results show an overall speed reduction, caused by the transistor drain current drop, and a leftward shift of the inverter voltage transfer characteristics, due to a larger degradation of the PMOSFET as compared to the NMOSFET. We attribute this behavior to the build-up of defects/trapped charge featuring a different kinetics in P- and N-type MOSFETs.     

Digital characteristics of a CMOS ternary inverter at the liquid nitrogen temperature

Static and dynamic performance of a CMOS ternary inverter has been studied in the MOSFET's threshold voltage region at the liquid nitrogen temperature (77K), and compared with the corresponding room temperature (296K) operation. It is observed that the positive ternary inverter (PTI), simple ternary inverter (STI) and negative ternary inverter (NTI) exhibit sharper voltage transfer characteristics and improved transient response at the liquid nitrogen temperature.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.