Quasi-static RAM design for high performance operation at liquid nitrogen temperature

The leakage currents which cause information loss in dynamic random access memories (DRAMs) at room temperature disappear at liquid nitrogen temperature, permitting operation of the circuits without the need for refresh (quasi-static operation). The current drive characteristics of the MOS transistor also improve significantly at liquid nitrogen temperatures. Combining these factors leads to an exploration of high speed dynamic RAM design based upon cells with non-destructive readout. This paper describes an experimental high speed RAM based upon a new two-transistor (2T) memory cell designed to exploit the unique advantages of operation at low temperature. Non-destructive readout coupled with a large d.c. sensible output current yields a high speed RAM with low power consumption. An experimental 4 kbit memory, fabricated using a 2 μm CMOS technology, exhibits an access time of 7 nS at 77 K.     

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed-pattern noise reduction

A novel logarithmic response CMOS image sensor fabricated by 0.25-/spl mu/m CMOS logic process is proposed. The new cell has an output voltage swing of 1 V in the targeted illumination range, which makes it less susceptible to noises in the readout system. Furthermore, the proposed new cell with in-pixel CDS control drastically reduces the fixed pattern noise in logarithmic mode CMOS APS. Comparing with a conventional pixel, a reduction of 10 times in fixed-pattern noise is demonstrated in the new logarithmic response CMOS image sensor.     

A Snapshot CMOS Image Sensor With Extended Dynamic Range

In this paper, a proof of concept for a snapshot CMOS image sensor with extended dynamic range is presented. A prototype of 32 times 32 pixels has been fabricated using the 1-poly 4-metal CMOS 0.35 mum process available through MOSIS and was successfully tested. The measurements from the test chip showed that the fabricated imager allows wide dynamic range (WDR) operation in a snapshot readout mode. This DR extension has become possible due to a unique in-pixel architecture allowing automatic adaptation of each pixel in the array to its illumination level. To reduce the pixel power dissipation various low-power design techniques have been utilized in the pixel design. A single pixel occupies 18 * 18(mum)² and dissipates 23 nW with 8 bit DR expansion at room light level, and 29 nW at high illumination level, equivalent to clear sky at video rate. The power dissipation of the whole sensor (including the supporting circuitry) is 450 muW at video rate. Sensor design is described, design considerations are shown and measurements from the test chip are presented.     

Performance of a radiation hard 128 channel analogue front-end chip for the readout of a silicon-based hybrid photon detector

The performance is described of a front-end chip, the SCT128A-LC chip, originally developed for the readout of a silicon based Hybrid Photon Detector (HPD), which is part of an RICH detector to be run in an LHC experimental environment. The relatively low signal charge from single photoelectrons, impinging on the silicon pad sensor, put very stringent requirements on the noise performance of the front-end chip. An absolute noise calibration using X-ray sources and a ²⁴¹Am γ source was performed. It is demonstrated that sufficiently good signal over noise ratio can be obtained to use this chip for the read-out of an HPD in LHC experiments.     

Compact CMOS current conveyor for integrated NEMS resonators

A fully integrated nanoelectromechanical system (NEMS) resonator together with a compact built-in complementary metal-oxide-semiconductor (CMOS) interfacing circuitry is presented. The proposed low-power second generation current conveyor circuit allows measuring the mechanical frequency response of the nanocantilever structure in the megahertz range. Detailed experimental results at different DC biasing conditions and pressure levels are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing based on nanostencil lithography. The proposed readout circuit can be adapted to operate the nanocantilever in closed loop as a stand-alone oscillator.     

Optical efficiency of image sensor pixels

The ability to reproduce a high-quality image depends strongly on the image sensor light sensitivity. This sensitivity depends, in turn, on the materials, the circuitry, and the optical properties of the pixel. We calculate the optical efficiency of a complementary metal oxide semiconductor (CMOS) image sensor pixel by using a geometrical-optics phase-space approach. We compare the theoretical predictions with measurements made by using a CMOS digital pixel sensor, and we find them to be in agreement within 3%. Finally, we show how to use these optical efficiency calculations to trade off image sensor pixel sensitivity and functionality as CMOS process technology scales.     

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

In this paper, a pixel structure called the optimal pseudoactive pixel sensor (OPAPS) is proposed and analyzed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling circuits are also used to suppress fixed-pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352/spl times/288 (CIF) has been designed and fabricated by using 0.25-/spl mu/m single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 /spl mu/m/sup -2/. The fabricated OPAPS CMOS imager has a pixel size of 8.2/spl times/.2 /spl mu/m, fill factor of 42%, and chip size of 3630/spl times/3390 /spl mu/m. Moreover, the measured maximum frame rate is 30 frames/s and the dark current is 82 pA/cm/sup 2/. Additionally, the measured optical dynamic range is 65 dB. It is found that the proposed OPAPS structure has lower dark current and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus, the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.     

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

This paper proposes a new design of a highly stable and low-power static RAM (SRAM) cell using carbon nanotube FETs (CNTFETs) that utilizes different threshold voltages for best performance. In a CNT, the threshold voltage can be adjusted by controlling the chirality vector (i.e., the diameter). In the proposed six-transistor SRAM cell design, while all CNTFETs of the same type have the same chirality, n-type and p-type transistors have different chiralities, i.e., a dual-diameter design of SRAM cell. As figures of merit, stability, power dissipation, and write time are considered when selecting the chirality for the best overall performance. A new metric, denoted as “SPR,” is proposed to capture these figures of merit. This metric shows that a CNTFET-based SRAM cell provides an “SPR” that is four times higher than for its CMOS counterpart that has the same configuration, thus attaining superior performance. Finally, the sensitivity of the CNTFET SRAM design to process variations is assessed and compared with its CMOS design counterpart. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based SRAM cell due to variations in the diameter, supply voltage, and temperature of the CNTFETs. The CNTFET-based SRAM cell demonstrates that it tolerates the process, power supply voltage, and temperature variations significantly better than its CMOS counterpart.      

Low-complexity low-memory energy-efficient image coding for wireless image sensor networks

Wireless image sensor networks are capable of sensing, processing and transmitting the image in hard-to-access regions without expensive network infrastructure and will have great contribution in Internet of Things. These networks are resource constraint systems with limited memory, energy, processing speed and bandwidth. Low computational energy and communication energy will improve the lifetime of these resource-limited networks. In this paper, an energy-efficient low-memory and low-bitrate image coding is designed exclusively for low-power camera-equipped sensor node. The performance of the proposed image coder is analysed in terms of bitrate, image quality, memory size and energy consumption. Experiments are carried out with Atmel ATmega128 processor. The experimental results show that this system consumes only 0.23% of energy consumed by true Discrete Cosine Transform-based Joint Photographic Experts Group (JPEG) standard and offers reasonable image quality suitable for visual perception at low bitrate. This system requires only 19% of memory required by standard JPEG.     

Liquid-phase chemical and biochemical detection using fully integrated magnetically actuated complementary metal oxide semiconductor resonant cantilever sensor systems

A novel resonant cantilever sensor system for liquid-phase applications is presented. The monolithic system consists of an array of four electromagnetically actuated cantilevers with transistor-based readout, an analog feedback circuit, and a digital interface. The biochemical sensor chip with a size of 3 mm x 4.5 mm is fabricated in an industrial complementary metal oxide semiconductor (CMOS) process with subsequent CMOS-compatible micromachining. A package, which protects the electrical components and the associated circuitry against liquid exposure, allows for a stable operation of the resonant cantilevers in liquid environments. The device is operated at the fundamental cantilever resonance frequency of approximately 200 kHz in water with a frequency stability better than 3 Hz. The use of the integrated CMOS resonant cantilever system as a chemical sensor for the detection of volatile organic compounds in liquid environments is demonstrated. Low concentrations of toluene, xylenes, and ethylbenzene in deionized water have been detected by coating the cantilevers with chemically sensitive polymers. The liquid-phase detection of analyte concentrations in the single-ppm range has been achieved. Furthermore, the application of this sensor system to the label-free detection of biomarkers, such as tumor markers, is shown. By functionalizing the cantilevers with anti-prostate-specific antigen antibody (anti-PSA), the corresponding antigen (PSA) has been detected at concentration levels as low as 10 ng/mL in a sample fluid.     

A CMOS sensor optimized for laser spot-position detection

An optical sensor architecture optimized for flying-spot, triangulation-based, three-dimensional (3-D) laser scanners will be presented. The architecture implements a spot-position detection algorithm based on a two-step procedure that allows for improved dynamic range and readout speed. The sensor, which contains two linear arrays of pixels, analog readout channels, and digital signal preprocessing circuitry, has been fabricated in 0.6-/spl mu/m CMOS double-poly triple-metal technology and measures 8.17/spl times/5.67 mm/sup 2/. Pixel size and shape have been selected for reducing the effect of laser speckle and for the possibility of measuring color in a multiwavelength 3-D scanner. Electrooptical test results confirm the sensor behavior as expected from simulations on a dynamic range of 80 dB and exhibits a maximum speed of 50-k voxel/s.     

Polarization holographic high-density optical data storage in bacteriorhodopsin film

Optical films containing the genetic variant bacteriorhodopsin BR-D96N were experimentally studied in view of their properties as media for holographic storage. Different polarization recording schemes were tested and compared. The influence of the polarization states of the recording and readout waves on the retrieved diffractive image's intensity and its signal-to-noise ratio were analyzed. The experimental results showed that, compared with the other tested polarization relations during holographic recording, the discrimination between the polarization states of diffracted and scattered light is optimized with orthogonal circular polarization of the recording beams, and thus a high signal-to-noise ratio and a high diffraction efficiency are obtained. Using a He-Ne laser (633 nm, 3 mW) for recording and readout, a spatial light modulator as a data input element, and a 2D-CCD sensor for data capture in a Fourier transform holographic setup, a storage density of 2 x 10(8) bits/cm2 was obtained on a 60 x 42 microm2 area in the BR-D96N film. The readout of encoded binary data was possible with a zero-error rate at the tested storage density.     

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.     

An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter

We present a direct-to-digital capacitive sensor readout circuit that converts capacitance changes of a sensor element to changes of the duty cycle of a square-wave oscillator, which, in turn, is converted to a digital output by a counter. The readout circuit resembles a single-slope analog-to-digital converter structure. There are several advantages of this readout scheme. First, due to its simplicity and low number of components, the power consumption of the circuit is expected to be significantly smaller than in similar digital readout designs. Furthermore, linearization of the output may be achieved using an EEPROM lookup table. Another advantage is the possibility of performing adaptive measurements where the sensor resolution and bandwidth may be changed via the readout circuit software. Finally, we present a theory of the adaptive measurement and an analysis of the design tradeoffs. The capacitance-to-duty cycle readout circuit may achieve large bandwidth and high resolution in a modern low-voltage, low-power CMOS implementation. The performance of a prototype readout circuit built from discrete components is 13-bit effective resolution with a 1-kHz bandwidth.     

Low-power 2-D fully integrated CMOS fluxgate magnetometer

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works using the single-core principle, with a modulation technique to lower the noise and the offset at the output. In contrast to traditional fluxgate approaches, the sensor features a high degree of integration and minimal power consumption at 2.5 V of supply voltage that makes it suitable for portable applications. A novel digital feedback principle is integrated to linearize the sensor characteristics and to extend the linear working range.     

VIKING, a CMOS low noise monolithic 128 channel frontend for Si-strip detector readout

A low noise Si-strip detector readout chip has been designed and built in 1.5 μm CMOS technology. The chip is optimized w.r.t. noise. Measurements with this chip connected to several silicon strip detectors are presented. A noise performance of ENC = 135 e⁻ + 12 e⁻/pF and signal to noise ratios between 40–80, depending on the detector, for minimum ionizing particles traversing silicon has been achieved.     

Autonomous Sensor System With Power Harvesting for Telemetric Temperature Measurements of Pipes

In this paper, an autonomous sensor system, with low-power electronics for radio-frequency (RF) communication, incorporating a thermoelectric energy-harvesting module for unattended operation is presented. A target application is proposed for temperature measurement of walled-in pipes. When the autonomous sensor is placed on the heat source, a thermoelectric module harvests energy, powering the autonomous sensor. In this condition, no external power source is necessary, the temperature measurement is performed, and the data are saved into a nonvolatile memory. When the external readout unit is active, the electromagnetic field is used to power the autonomous sensor system and to communicate the data. An experimental setup has been arranged and characterized by measuring the temperature along the pipe, the voltage that can be generated by thermoelectric generators, and the influence of different materials on RF communication. The temperature data of the heat source, which are collected by the autonomous sensor, are compared with that of a reference thermistor. The measurement results show good agreement between the two measured temperature data sets. The experimental data demonstrate that the autonomous system works correctly for a temperature gradient that is higher than 9degC, within a readout distance of a few centimeters. The presented autonomous sensor system can be effectively used for measurements into a close environment in which a temperature difference is present.     

双极型光栅晶体管的瞬态特性模型及模拟分析

提出一种应用于CMOS图像传感器的新型光电检测器件-双极型光栅晶体管，并建立了其瞬态等效电路模型，利用电路模拟软件HSPICE的多瞬态分析法对双极型光栅晶体管的光电流特性进行了仿真，分析得出这种新型器件在0.6μmCMOS工艺参数下，由于引入pn注入结加速了光电荷的读出速率，光电流随外加电压呈指数式增长，与普通光栅晶体管相比，蓝光响应特性有较大改善。     

High-resolution interline image sensors using two-phase CCD technology

Two interline, 30 frames/second, high-resolution image sensors are described that use two-phase charge coupled device (CCD) technology. One is a two-megapixel, interlaced high-definition television, sensor, and the other is a 1-megapixel, progressive-scan sensor for machine vision applications. These sensors include features such as dual-horizontal CCD readout, antiblooming protection, electronic shutter capability, low smear, and no lag.©1994 John Wiley & Sons Inc     

A vision-based DSP embedded navigation sensor

Spacecraft missions such as spacecraft docking and formation flying require high-precision relative position and attitude data. Deep space missions require the use of alternative technologies. One such technology is the vision-based navigation (VISNAV) sensor system developed at Texas A&M University. VISNAV comprises an electro-optical sensor combined with light sources or beacons. This patented sensor has an analog detector in the focal plane with a rise time of a few microseconds. Accuracies better than one part in 2000 of the field of view have been obtained. Simultaneous activation of beacons with frequency division multiplexing is given as part of the VISNAV sensor system. The synchronous demodulation process uses digital heterodyning and decimating filter banks on a low-power fixed point digital signal processor, which improves the accuracy of the sensor measurements and the reliability of the system. This paper also presents an optimal and computationally efficient six-degree-of-freedom estimation algorithm using a new measurement model based on the attitude representation of modified Rodrigues parameters.