BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers

A BiCMOS dynamic minimum circuit using a parallel comparison algorithm for the VLSI implementation of fuzzy controllers is presented. Using BiCMOS dynamic circuits and a parallel comparison algorithm a four 4-bit-input minimum circuit, designed based on a 2 mu m BiCMOS technology shows a 7.4 ns comparison time, which is a *3 improvement in speed as compared with the CMOS circuit. In addition, this circuit has an expansion capability for realising large-scale minimum circuits.<>     

Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

A BiCMOS dynamic multiplier using Wallace tree reductionarchitecture and 1.5-V full-swing BiCMOS dynamic logic circuit

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one     

Integrated circuit implementation of fuzzy controllers

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno's method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 b is achieved. The connection of these blocks according to a proposed architecture allows fuzzy chips with low silicon area whose inference speed is in the range of 2 Mega FLIPS (fuzzy logic inferences per second),     

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable forVLSI using low-voltage BiCMOS technology

This paper presents a 1.5 V full-swing BiCMOS dynamic logic gate circuit, based on a dynamic pull-down BiPMOS configuration, suitable for VLSI using low-voltage BiCMOS technology. With an output load of 0.2 pf, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable     

Modular current-mode multiple input minimum circuit for fuzzy logiccontrollers

A new current-mode multiple input minimum circuit designed with 4n+1 transistors for n inputs is proposed. Not only is the problem of accumulated errors solved, but the operation speed is also increased owing to the proposed multiple input minimum circuit having a one stage structure. This circuit had been fabricated using 0.8 μm CMOS technology. Experimental results have verified the function of the circuit and shown the merit of high accuracy and a large dynamic range     

一种低压BiCMOS四象限模拟乘法器的设计

提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。     

Low-voltage electronics for the stimulation of biological neuralnetworks using fully complementary BiCMOS circuits

This paper describes low-voltage neural stimulating circuitry developed using fully complementary BiCMOS (FC-BiCMOS) process technology for providing charge-balanced bipolar stimulating currents to tissue in the central nervous system. The electronics features an FC-BiCMOS buffer, a 7-b biphasic current-output digital-to-analog converter, a 14-b frequency divider, a nonoverlapping two-phase clock generator, and an auto timeout safety scheme while driving any two of eight selected sites from 0 to ±126 μA with ±2 μA resolution. The circuit area is 1.6 mm² in 3-μm features. Micropower circuit techniques allow the probe to dissipate <10 μW in standby and operate at 10 MHz from ±2.5 V supplies     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-μm BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

Optimal and stable fuzzy controllers for nonlinear systems based on an improved genetic algorithm

This paper addresses the optimization and stabilization problems of nonlinear systems subject to parameter uncertainties. The methodology is based on a fuzzy logic approach and an improved genetic algorithm (GA). The TSK fuzzy plant model is employed to describe the dynamics of the uncertain nonlinear plant. A fuzzy controller is then obtained to close the feedback loop. The stability conditions are derived. The feedback gains of the fuzzy controller and the solution for meeting the stability conditions are determined using the improved GA. In order to obtain the optimal fuzzy controller, the membership functions are further tuned by minimizing a defined fitness function using the improved GA. An application example on stabilizing a two-link robot arm will be given.     

1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture

A 1.5V BiCMOS dynamic multiplier is presented which is free from race and charge sharing problems, using Wallace tree reduction architecture and a 1.5V full-swing BiCMOS dynamic logic circuit. Based on a 1 mu m BiCMOS technology, a designed 1.5V 8*8 multiplier shows a *2.3 improvement in speed as compared to the CMOS static multiplier.<>