A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-μm triple-metal CMOS process and occupies a die area of 0.45 mm². Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply     

Clock distribution scheme for high-speed DRAM

A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results show that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage, and temperature variations     

A high-speed shuffle bus for VLSI arrays

A high-speed shuffle bus which is able to implement various kinds of communication schemes for VLSI processor arrays is presented. Because of the simple and modular nature of the shuffle bus, the processor arrays can now be easily modularized and equipped with flexible capabilities for both global and neighboring communications. With data swapping at a rate as high as 200 MHz between adjacent registers, the shuffle bus is about 20 times faster than those bidirectional pipelined buses. The shuffle bus may be expanded to accommodate any number of nodes with an arbitrary number of bits in each word. With only a few sets of control patterns, the shuffle bus can be applied to the implementation of a wide variety of interconnection networks, sorting networks, FIFO, and associative memory     

A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-μm DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz     

A monolithic high-speed sample-and-hold amplifier for digital audio

A monolithic high-speed sample-and-hold amplifier is described which has an acquisition time of 1.5 /spl mu/s to 0.001% for a 10-V step and an aperture uncertainty of less than 0.5 ns. Distortion is 0.001% over the audio band, while in an A/D and D/A converter loop a signal-to-noise ratio better than 90 dB is measured. Chip size is 1.5/spl times/2.5 mm/SUP 2/.     

一种加速DRAM灵敏放大器的设计方法

文章设计了一种DRAM中的灵敏放大器,通过增加一个过充电压开关,一个过充电压工作时间脉冲控制电路,一个发生器电路,使得灵敏放大器的放大速度有效提升,从而改善了DRAM的性能指标参数t RCD,提高了DRAM的性能。这种方法通过很小的代价,实现了灵敏放大器放大速度的改进。电路易于控制,版图面积增加很小,功耗无需增加,是一种提高灵敏放大器性能的有效方法。     

A novel high-speed sense amplifier for Bi-NOR flash memories

A novel high-speed current-mode sense amplifier is proposed for Bi-NOR flash memory designs. Program and erasure of the Bi-NOR technologies employ bi-directional channel FN tunneling with localized shallow P-well structures to realize the high-reliability, high-speed, and low-power operation. The proposed sensing circuit with advanced cross-coupled structure by connecting the gates of clamping transistors to the cross-coupled nodes provides excellent immunity against mismatch compared with the other sense amplifiers. Furthermore, the sensing times for various current differences and bitline capacitances and resistances are all superior to the others. The agreement between simulation and measurement indicates the sensing speed reaches 2ns for the threshold voltage difference of lower than 1 V at 1.8-V supply voltage even with the high threshold voltage of the peripheral CMOS transistors up to 0.8 V.     

An open-loop clock deskewing circuit for high-speed synchronous DRAM

An open-loop clock deskewing circuit (CDC) for high-speed synchronous DRAM is described. Unlike the conventional circuits, the CDC does not require an additional measure delay line, thus power consumption is reduced. The delay is measured directly from the main delay line and both the input and output ports of the delay line are movable. The CDC provides a deskewed clock within two clock cycles.     

An analog synchronous mirror delay for high-speed DRAM application

An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-μm double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1×0.7 mm² . An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps±200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input     

ASMD with duty cycle correction scheme for high-speed DRAM

An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

一种适应于flash memory的超低压和高速的感应放大器设计

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct current-mode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 μ A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.     

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented,based on a very simple direct current-mode comparison.It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage,low power and high precision.The proposed amplifier can sense a 0.5μA current gap and work with a lowest voltage of 1V.In addition,the current power of a single amplifier is optimized by 15%.     

Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

A novel bitline sensing scheme is proposed for low-voltage DRAM to achieve low power dissipation and compatibility with low-voltage CMOS. One of the major obstacles in low-voltage DRAM is the degradation of data-retention time due to low signal level at the memory cell, which requires power-consuming refresh operations more frequently. This paper proposes an offset-cancellation sense-amplifier scheme (OCSA) that improves data-retention time significantly even at low supply voltage. It also improves die efficiency, because the proposed scheme reduces the number of sense amplifiers by supporting more cells in each sense amplifier. Measurements show that the data-retention time of the proposed scheme at 1.5-V supply voltage is 2.4 times of the conventional scheme at 2.0 V.     

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.<>     

High-speed charge transfer sense amplifier for 0.5 V DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.     

A tiny, high-speed, wide-band, voltage-feedback amplifier stablewith all capacitive load

A tiny, high-speed, wide-band, voltage-feedback operational amplifier capable of driving unlimited capacitive load is described. A class AB input stage is combined with a modified dynamic Witch-Hazel current mirror to provide high slew rate and wide bandwidth with a small die area and small idle current. An RC network couples part of the capacitive load into the high-impedance node, therefore lowering the dominant pole and increasing stability as a function of capacitive load. The part was fabricated on a 3 GHz, 40 V complementary bipolar process. The quiescent current of the chip is 4.5 mA with 1500 V/μm slew rate and a -3 dB bandwidth of 235 MHz. The part is operational from ±2.5 V to ±18 V supply range. Die size is 38 mils by 46 mils and it fits into a tiny surface outline transistor (SOT) package     

A high-speed current-multiplexed sample-and-hold amplifier with lowhold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm² on a junction-field-effect-transistor (JFET) plus complementary bipolar process     

Scalable high-power, high-speed CW VCSEL arrays

A demonstration of a high-power, high-speed 980 nm vertical-cavity surface-emitting laser array with continuous-wave power of greater than 120 mW and frequency response over 7.5 GHz at room temperature is reported. Experimental results show that copper plating the array elements and flip-chip bonding provides effective thermal management as well as offering uniform current distribution at microwave frequencies. This is verified by the radial dependence of modulation bandwidth. These arrays may be useful for short-range light detection and ranging or free-space optical communications systems.     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology