A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with datarecovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-μm HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3× the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10^-14     

Statistical Performance Analysis of an Interframe Encoder for Broadcast Television Signals

This paper desribes an objective evaluation for coding performance of an interframe encoder (NETEC-22H). Also described is the coding performance improvement by an adaptive bit sharing multiplexer (ABS-MUX) in which transmission bit rate is dynamically allocated to several channels. Measurements made for actual broadcast TV programs over a time of 36 h show that an SNR of higher than 50 dB unweighted is obtained by this coding equipment for 99 percent of the time for broadcast TV programs at the transmission bit rate of 30 Mbits/s and for 93 percent of the time at 20 Mbits/s. The residual 1 percent at 30 Mbits/s or 7 percent at 20 Mbits/s is transmitted with a slightly lower SNR. The picture quality difference between the 20 and 30 Mbit/s transmission is about 6 dB in SNR on the average. It is also shown that a three-channel ABS-MUX (20 Mbits/s per channel on the average) reduces probability of coarse quantization by a factor of 5-10 compared with the fixed bit rate transmission at 20 Mbits/s.     

超宽带延时幅相控制多功能芯片的设计

针对航空航天和卫星通信等设备的需求,介绍了一款超宽带延时幅相控制多功能芯片。该芯片集成了数字和微波电路,有T/R 开关、5 位数控延时器(10 ps 步进TTD)、5位数控衰减器(1 dB 步进ATT)、2 个行波放大器、均衡器及数字电路。基于GaAs E/D PHEMT 工艺研制出了芯片实物,芯片尺寸为4.5 mm*5.0 mm*0.07 mm。采用微波在片测试系统对该幅相控制多功能芯片进行了实际测试,在3 ~ 17 GHz 频段内实现了10~310 ps 延时范围,1~31 dB 衰减范围。测试结果显示,发射/接收增益大于2 dB,发射1 dB 压缩输出功率P1 dB_Tx大于12 dBm,接收1 dB 压缩输出功率P1 dB_Rx大于10 dBm,全态输入输出驻波均小于1.7,+5 V 下工作电流130 mA,-5 V 下工作电流12 mA。衰减器全态RMS 精度小于1.4 dB,全态附加调相小于±8°。延时器全态RMS 精度小于3 ps,全态附加调幅小于±1 dB。     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively     

A 12-bit 1.0/2.0 GS/s Pipeline ADC in 0.18 µm SiGe BiCMOS

A 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.     

A multi-D trellis decoder for A 155 Mb/s concatenated codec

An implementation of a 16 state, rate 8/9 six-dimensional (6-D) 8PSK rotationally invariant trellis decoder for use in a concatenated codec is described. The concatenated codec allows transmission of STM-1 signals (at the 155.52 Mb/s information rate) over a 72 MHz satellite transponder. The inner trellis decoder is used with an outer (255,239) RS block decoder. The trellis decoder operates at 165.93 Mb/s and currently has an implementation loss of only 0.2 dB. The concatenated codec achieves a bit error ratio of 10^?10 at an Eb/N⁰ of 8.2 dB (assuming an ideal modem and AWGN channel). Details are given of many Viterbi decoding ‘tricks’ that were used in order to implement the main functions of the decoder on two 10,000 gate equivalent CMOS programmable gate arrays.     

A digital coherent receiver suitable for land-mobile satellitecommunications

Describes an advanced coherent demodulation technique suitable for land-mobile satellite communications. The proposed technique features a combined narrow/wide band dual open loop (DOL) carrier phase estimator, which effectively enables the coherent receiver to track fast phase fluctuations caused by fading, without degradation in phase slip characteristics. Additionally, an open loop phase estimator has inherent quick recovery performance. Its bit error rate (BER) performance is shown to be superior to that for existing detection schemes, achieving a 10^-2 BER at 6.3 dB E_b/N₀ (0.9 dB greater than the theoretical E_b/N₀ condition for perfect carrier phase tracking) for QPSK over a Rician fading channel with the 10 dB Rician factor and the 1/16 baud rate fading pitch. The paper also describes a quick bit timing recovery scheme, with interpolation, featuring an open loop structure. Further, it presents an experimental digital modem developed through the use of digital signal processors     

An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.     

Optoelectronic switches and multigigabit 8:1 time multiplexer

Optoelectronic metal-semiconductor-metal (MSM) switches in InP were studied and used as sampling elements in a digital time division multiplexer. It was found that switch performance can range from the depletion-layer photodiode to the photoconductor regime as the activating light intensity increases. The multiplexer had an 8:1 ratio, a 2-V signal bias, >25-dB S/N, and a serial rate of at least 2.5 Gb/s. This multiplexer with its high S/N and the timing stability intrinsic to fiber delay lines will be advantageous for high-speed digital communications     

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 ${hbox{mm}}^{2}$ in a 90 nm 1P9M digital CMOS process.      

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

8 GHz, 10 W solid-state power amplifier for microwave digital radio

An 8 GHz, 10 W GaAs FET prototype power amplifier has been developed to replace the TWT in the Northern Telecom's digital microwave radio system. For a single bit stream of 91.04 Mbit/s, the residual bit error rate at 40 dBm output level was 1.0×10?32 compared with 1.0×10?23 for TWT; the AM/AM conversion ratio was 0.375 dB/dB and AM/PM was 0.84°/dB. The total mean time between failure of the amplifier was 350 000 h.     

A novel 1×4 coupler-multiplexer permutation switch for WDMapplications

A novel 1×4 coupler multiplexer permutation switch (CMPS) is proposed for applications in wavelength-division-multiplexing (WDM) optical networks. The structure of the CMPS integrates the multiplexing and switching functions into a single compact device. It consists of a single-mode/multimode-waveguide grating-assisted, backward-coupler multiplexer followed by a 1×4 digital optical switch (DOS). The specific design uses an InP-based 1×4 CMPS with InGaAsP-InP multiple-quantum-well (MQW) DOS. The calculated values of crosstalk for the coupler multiplexer and the DOS are <-25 dB and -23 dB, respectively, giving an overall crosstalk <-21 dB for channel bandwidths of 10-13 GHz. The device channels are unequally spaced, which reduces unwanted four-wave mixing (FWM), but are fitted to the ITU standard wavelength grid     

Delay-Line-Based Analog-to-Digital Converters

We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm²) and small power consumption (<2.4 mW).     

2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

Frequency division multiplexed microwave and baseband digitaloptical fiber link for phased array antennas

A frequency-division multiplexed optical fiber link is described in which microwave (1-8 GHz) and baseband digital (1-10 Mb/s) signals are combined electrically and transmitted through a direct-modulation microwave optical link. The microwave signal does not affect bit error rate (BER) performance of the Manchester-coded baseband digital data link. The baseband digital signal affects microwave signal quality by generating second-order intermodulation noise. The intermodulation noise power density is found to be proportional to both the microwave input power and the digital input power, enabling the system to be modeled as a mixer (AM modulator). The conversion loss for the digital signal is approximately 68 dB for a 1-GHz microwave signal and is highly dependent on the microwave frequency, reaching a minimum value of 41 dB at 4.5 GHz corresponding to the laser diode relaxation oscillation frequency. It is shown that Manchester coding on the digital link places the intermodulation noise peak away from microwave signal, preventing degradation of close-carrier phase noise (<1 kHz offset). A direct trade-off between intermodulation noise and digital link margin is developed to project system performance     

26GS/s单bit量化降速芯片

基于1μm GaAs HBT工艺设计并实现了一种26GS/s单bit量化降速芯片。芯片采用树形级联架构,集成前端宽带比较器,综合优化各级降速单元拓扑,在功耗、速度各方面达到最优化。测试结果表明,芯片在26GS/s转换速率下,其SFDR大于8dBc,数据带宽达13GHz,显示出其在电子对抗及高速数据处理方面的潜力。     

MPEG-2数字视频广播传输流中节目参考时钟的处理

MPEG 2标准系统层中定义的传输流已经在事实上成为数字电视领域中系统层传输的普遍标准。数字视频广播系统中传输流的处理由复用器完成。由于节目参考时钟是编解码器中共同系统时钟的标签 ,精确度要求非常严格 ,因此复用器研制的一个难点就是节目参考时钟的处理。文中利用复用器的传输流输出端对节目参考时钟进行精确插入 ,充分利用了数字信号处理器和 9位先入先出缓存的特性 ,精确而简易地满足了数字视频广播系统的时序要求。