Method of fabricating high-Q silicon varactor diodes

A new processing technique has been developed for the fabrication of high-Q and high-voltage varactor diodes. The process utilises ion implantation and laser annealing for heavily-doped p++ and n++ layers and epitaxial growth for low impurity concentrations. The technique provides good yield and repeatability, and it has allowed fabrication of varactor diodes which have breakdown voltages of 120 V and a Q as high as 600 at ?8 V bias and 50 MHz frequency.     

电铸在LIGA技术中的应用

近年来，电铸在微细加工中的应用得到了较快发展，尤其在近几年高速发展的ＬＩＧＡ技术的掩模加工和其应用产品中，该技术充分体现出了字的优越性能和潜在的应用前景。本文结合ＬＩＧＡ技术掩模的加工及其电铸产品，用已取得的实验结果来说明电铸的应用潜力。     

Fabrication and Performance of Color Filter Arrays for Solid-State Imagers

A technique has been developed for the fabrication of a color filter array (CFA) to be used in conjunction with a solid-state area sensor to provide three-color image information from a single sensor. The fabrication technique employs sublimable dyes which are heat-transferred through photoresist windows onto a polymer receiving layer. Good edge sharpness and a low dye penetration depth into the polymer have been achieved. The predicted and measured spectral response of the color channels of the composite device are in good agreement. The pattern noise associated with CFA transmittance fluctuations from element to element is on the order of 10 percent.     

Fabrication and performance of color filter arrays for solid-state imagers

A technique has been developed for the fabrication of a color filter array (CFA) to be used in conjunction with a solid-state area sensor to provide three-color image information from a single sensor. The fabrication technique employs sublimable dyes which are heat-transferred through photoresist windows onto a polymer receiving layer. Good edge sharpness and a low dye penetration depth into the polymer have been achieved. The predicted and measured spectral response of the color channels of the composite device are in good agreement. The pattern noise associated with CFA transmittance fluctuations from element to element is on the order of 10 percent.     

半导体断路开关(SOS)特性研究

本文描述了半导体断路开关(SOS)的制作及性能测试。制作方法采用普通二极管类似的扩散工艺．但其制作工艺的关键在于深结的扩散。在pn结足够深时才能产生SOS效应。描述了制作过程并采用脉冲电路测试了所研制的SOS器件的电学性能。测试结果表明所研制的样品性能达到了与国外水平。     

Experimental and theoretical analysis of argon plasma-enhanced quantum-well intermixing

Plasma-enhanced quantum-well intermixing (QWI) has been developed for tuning the bandgap of InGaAs-InP material using an inductively coupled plasma system. The application of inductively coupled plasma enhances the interdiffusion of point defects resulting in a higher degree of intermixing. Based on a semi-empirical model of QW interdiffusion, the bandgap blue-shift with respect to the plasma exposure time and inductively coupled plasma energy has been analyzed. The theoretical results appear to be in good agreement with the experimental data of the intermixed samples. The model serves as a good simulation tool to explain the intermixing mechanism and further to optimize the intermixing process for the fabrication of the photonic integrated circuits.     

InP/空气隙结构的制作与特性

研究了采用不同溶液制作InP/空气隙的侧向腐蚀工艺,对腐蚀速率、晶向选择性、表面形貌进行了分析;研究了粘附释放工艺;在上述基础上制作完成了InP/空气隙结构,并采用微拉曼光谱来分析其应力分布情况,证实了制作工艺的可靠性.     

Fabrication of 24-MHz-Disk Resonators With Silicon Passive Integration Technology

A new approach for the fabrication of large contour-mode single-crystal silicon resonators has been demonstrated without the use of SOI substrates. Twenty-four-megahertz disk resonators have been built thanks to industrial facilities dedicated to the integration of passive components on silicon and exhibit a good compromise between the quality factor higher than 50 000 and the motional resistance of a few kiloohms.     

Development of Stretch Solder Interconnections for Wafer Level Packaging

A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.     

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.      

埋入电镀电阻在高速线路中的应用

埋入电阻是实现高频电路的重要方法之一。现已开发出在内层要求精确电镀上电阻元件的工艺,这意味着PCB制造厂可采用各种类型层压板材料,根据不同电镀时间得到从25 Ω到100 Ω范围内的方块电阻值(电阻率),而不是采用各种不同电阻值金属箔的基材来制备不同阻值的埋入电阻。采用常规PWB的活化和化学镀等制造步骤便可制作这种电阻,这种埋入电阻工艺是易于激光检修并层压到多层板内部是很稳定的。这种埋入电阻经过多层层压,温度变化或者显露于潮湿环境下表明电阻值是很小改变的,经过模拟电路运作具有好的稳定性。     

Close-spaced fused fibre wavelength division multiplexers with very low polarisation sensitivity

The authors describe the fabrication of high performance narrowband fused fibre wavelength multiplexers. A twisting technique is employed to reduce the polarisation sensitivity. Unlike other polarisation quenching methods, twisting maintains the intrinsically good temperature stability of the device. The twisting mechanism has been studied theoretically using a model with a realistic coupler cross-section.<>     

铁电存储器制备中关键工艺的改进

传统铁电存储器制备工艺中,存在着Ｐｔ／Ｔｉ下电极刻蚀难、制作的铁电薄 貌不好和上电极容易起壳等问题。文章对铁电存储器制备中的一些关键工艺进行改进,降低了工艺复杂性,解决了上述问题。     

用腐蚀熔融法制造单模激光二极管与单模光纤相耦合的半球微透镜

近年来由于单模光纤研究的极大成功，促进了单模光纤通信系统和单模光纤应用技术的迅速发展。单模光纤的实际损耗已降到接近理论值，因此为进一步改善单模光纤传输系统的信噪比，提高激     

切丝重熔法制备的BGA焊球及其表面形貌

BGA及μBGA、CSP、MCM封装片及倒装片与基板的连接过程中,其关键与核心是钎料凸点的制作技术。制作这种凸点可以采用事先制作好的焊球,介绍了BGA焊球的实验室制备方法——切丝重熔法,用该方法可获得尺寸准确,表面质量较好的焊球。并对焊球颗粒的表面显微结构进行了分析。     

An evaluation of FUROX isolation technology for VLSI/nMOSFETfabrication

A defect-free near-zero bird's beak, fully recessed oxide (FUROX) field-isolation technology has been evaluated through the fabrication of VLSI/nMOSFETs. The FUROX process mainly consists of: (1) a thin nitrided oxide as the stress buffer layer and the interface sealing layer for local oxidation enhancement; and (2) a novel more-reliable nitride masking structure for a two-step field oxidation and a self-aligned field implantation. The elimination of the necking effect on positive photoresist and the improvement of critical dimension control for polysilicon gates using the planarized isolation have been demonstrated. Through electrical characterization of n⁺-p diodes and field and active transistors, the FUROX devices have been shown to provide low leakage-current level, good isolation property, and large recovery of the effective channel width (1.4 μm). Therefore, the serious narrow-width effects that exist in conventional LOCOS (local oxidation of silicon) isolated have been effectively reduced. Using histogram analysis, the reliability of the masking structure had hence good uniformity of device properties for FUROX isolation have been exhibited. The successful fabrication of FUROX devices with W_eff=0.6 μm clearly demonstrates that FUROX isolation technology is greatly superior to conventional LOCOS     

GaInAs junction FET fully dry etched by metal organic reactive ion etching technique

The metal organic reactive ion etching technique, which uses a mixture of methane, hydrogen and argon, has been applied for the first time to the fabrication of a device. This etching technique is used to define the gate of a GaInAs junction FET. Results shows that it permits good control of etching depth with low surface damage.     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Lateral Buckling of High Aspect Ratio Janus Nanowalls

In recent years, the fabrication of Janus materials and their potential applications has been of much interest in Materials Science. Here, we report the fabrication of an entirely novel structure–Janus nanowalls and the phenomenon of lateral buckling in them. Polymeric nanowalls were prepared with the replica molding technique and metal films, of comparable thicknesses, were then deposited on one side of the polymer nanowalls by vacuum process. During the metal deposition, the nanowalls themselves buckle laterally; this buckling is induced by the compressive residual stress in the metal film and geometric confining constraints. The feature of wrinkle patterns resulting from the lateral buckling was theoretically investigated using the scaling analysis. Theoretical results are in good agreement with the experimental observations.