面向微处理器验证的约束描述语言及其编译器

该文提出了一种用于微处理器体系结构级测试程序自动生成的约束描述语言,并设计实现了该语言的编译器,详细介绍了语言特性以及为了生成合法体系结构级测试程序,编译器所做的特殊处理。最后给出了利用该语言对DLX微处理器进行验证的实验和结果。     

数字电路描述语言及其编译实现中的一些问题

介绍了目前国际上通用的标准数字电路描述格式，并针对该格式的特点给出了一个对数字电路描述进行编译的方法。同时分析了编译实现中存在的一些难点并给出了解决问题的方法。最后给出了针对ＩＳＣＡＳ８９电路的实验结果。     

C编译器自动测试仿真研究

该文涉及的C编译器仿真自动测试的主要思想是在自动生成c编译器测试用例的设计中引入随机的思想和算法。一方面，用“任何测试点都可能测到”的思想代替“每个测试点都必须测到”的思想，从而在测试用例的数量达到一定规模时，在满足应用的条件下实现对编译器产品的正确性评估；另一方面，完全排除了人为因素对测试的影响。其另一关键思想是引入一个实践证明的成熟编译器作为参考编译器，让被测编译器和参考编译器在同样环境下运行同一组测试用例。然后对比运行结果，如有不同，即证明被测编译器有错误，这种模式，有效排除了预先给定运行结果的测试模式中人为因素对测试结果的影响。     

可重定向编译器中的体系结构描述与代码调度

采用了XML这种表达能力强,语法无二义的语占对体系结构进行描述,重点分析了编译器在代码调度阶段实现可重定向性的手段,以及体系结构描述如何高效地支持代码调度。     

共享内存结构并行程序的编译器优化

共享内存结构上的程序自动并行化通常实现循环级并行,采用fork-join执行模式,并行性能有待提高。论文结合fork-join和SPMD两种执行模式的优势,在并行化编译过程中通过并行区合并和扩展,实现fork-join和SPMD混合执行模式,并在SPMD并行区中实现了基于跨处理器相关图的barrier同步优化。分析验证表明,这些优化策略减少了并行区和barrier同步的数目,有效地提高了生成并行程序的性能。     

自适应策略描述语言编译器的设计与实现

复杂自适应系统中的软件实体既需要完成业务功能,又需要不断地感知环境,并根据环境的变化调整自己的结构和行为来适应环境,完成自适应功能。当前自适应系统的开发存在将自适应逻辑和业务逻辑相互缠绕的问题,使得自适应系统的开发和维护变得极为复杂和困难。本文将自适应系统中的自主运行单元抽象为自适应Agent,将自适应Agent的业务逻辑和自适应逻辑相分离,提出了表述Agent如何适应环境变化的自适应策略描述语言SADL。为了将自适应策略编译成可执行的程序单元,本文设计并实现了SADL编译器。通过案例分析阐述了如何定义自适应策略,并展示了编译结果,验证了方法的有效性。     

面向对象语言编译器的自动测试平台

提出了一种新的面向对象语言编译器自动测试的方法和过程,并在此基础上设计开发了面向对象编译器自动测试工具(O_OCTT)。测试用例的自动生成是编译器自动测试工具的核心,介绍了C 编译器测试用例自动生成的手段和方法,阐述了。O_OCTT设计与实现过程中的关键技术。     

编译基础设施中多目标编译技术探讨

从编译基础设施的基本概念出发，着重讨论了编译器后端构造所涉及的关键技术；比较全面地总结并评述了具有代表性的公共编译设施及春采用的中间表示技术、后端构造技术和相关工具；并探讨了编译器后端构造研究中存在的一些问题及相应的解决方案。     

Milepost GCC: Machine Learning Enabled Self-tuning Compiler

Tuning compiler optimizations for rapidly evolving hardware makes porting and extending an optimizing compiler for each new platform extremely challenging. Iterative optimization is a popular approach to adapting programs to a new architecture automatically using feedback-directed compilation. However, the large number of evaluations required for each program has prevented iterative compilation from widespread take-up in production compilers. Machine learning has been proposed to tune optimizations across programs systematically but is currently limited to a few transformations, long training phases and critically lacks publicly released, stable tools. Our approach is to develop a modular, extensible, self-tuning optimization infrastructure to automatically learn the best optimizations across multiple programs and architectures based on the correlation between program features, run-time behavior and optimizations. In this paper we describe Milepost GCC, the first publicly-available open-source machine learning-based compiler. It consists of an Interactive Compilation Interface (ICI) and plugins to extract program features and exchange optimization data with the cTuning.org open public repository. It automatically adapts the internal optimization heuristic at function-level granularity to improve execution time, code size and compilation time of a new program on a given architecture. Part of the MILEPOST technology together with low-level ICI-inspired plugin framework is now included in the mainline GCC. We developed machine learning plugins based on probabilistic and transductive approaches to predict good combinations of optimizations. Our preliminary experimental results show that it is possible to automatically reduce the execution time of individual MiBench programs, some by more than a factor of 2, while also improving compilation time and code size. On average we are able to reduce the execution time of the MiBench benchmark suite by 11% for the ARC reconfigurable processor. We also present a realistic multi-objective optimization scenario for Berkeley DB library using Milepost GCC and improve execution time by approximately 17%, while reducing compilation time and code size by 12% and 7% respectively on Intel Xeon processor.     

Testing Programs with the Aid of a Compiler

if finite input-output specifications are added to the syntax of programs, these specifications can be verified at compile time. Programs which carry adequate tests with them in this way should be resistant to maintenance errors. If the specifications are independent of program details they are easy to give, and unlikely to contain errors in common with the program. Furthermore, certain finite specifications are maximal in that they exercise the control and expression structure of a program as well as any tests can.     

结构化文本语言编译器的虚拟机指令设计与优化

针对自主开发 IEC61131结构化文本(ST)语言编译器的需求,设计了一套机器无关的虚拟机指令集,指令集按照数据传送、算术运算、逻辑运算、位操作、比较操作、流程控制、函数调用等类型划分,采用三地址码的四元式表示.基于该指令集,设计了结构化文本语言的 IF语句、FOR语句、CASE语句、EXIT语句的指令形成算法,编译器将结构化文本语言编译为二进制指令文件.针对FOR语句提出了"向上计数"、"向下计数"、"动态确定上下限"的3种翻译模式,针对CASE语句提出了基于短路求值和跳转表混合的翻译模式,可优化FOR语句、CASE语句的指令结构.对编译形成的二进制指令,采用常量折叠计算、代数简化、临时变量消除、引用点分析等手段,进一步优化指令.实验测试结果表明,优化后的指令在嵌入式工控装置中的解释执行时提升了效率.     

A Vectorizing Compiler for Multimedia Extensions

In this paper, we present an implementation of a vectorizing C compiler for Intel's MMX (Multimedia Extension). This compiler would identify data parallel sections of the code using scalar and array dependence analysis. To enhance the scope for application of the subword semantics, our compiler performs several code transformations. These include strip mining, scalar expansion, grouping and reduction, and distribution. Thereafter inline assembly instructions corresponding to the data parallel sections are generated. We have used the Stanford University Intermediate Format (SUIF), a public domain compiler tool, for our implementation. We evaluated the performance of the code generated by our compiler for a number of benchmarks. Initial performance results reveal that our compiler generated code produces a reasonable performance improvement (speedup of 2 to 6.5) over the the code generated without the vectorizing transformations/inline assembly. In certain cases, the performance of the compiler generated code is within 85% of the hand-tuned code for MMX architecture.     

A Pattern-Matching Compiler

Implementation of a rule-based transformation engine consists of several tasks with various abstraction levels. We present a new tool called mtom for the efficient implementation of rule-based transformations. This engine should help to bridge the gap between rewriting implementations and practical applications. It aims at implementing well-identified parts of complex applications where the use of rewriting is natural or crucial. These parts are specified using rewrite rules and integrated with the rest of the application, which is kept in a classical imperative language such as C, C++ or Java. Our tool, which can be viewed as a Yacc-like pre-processor, does not depend on a given term representation, rather it accepts implementation of terms (or term like data-types) of yet existing applications and it permits to define and execute rewrite rules upon those types. From our experiences, this system is well-suited for industrial use as well as for implementations of rule-based languages. The paper introduces several features supported by mtom.     

一种支持DSP条件执行指令的编译框架

为克服条件跳转指令的缺陷,新一代超长指令字（VLIW）体系结构的数字信号处理器（DSP）提供了对条件执行指令的支持。为使得此类指令的优势得以充分发挥,该文设计并实现了一种基于hyperblock区域结构的编译框架。实验结果表明,该框架很好地提高了指令级并行虚（ILP）,减少了指令执行时间。     

A Compiler Intermediate Representation for Reconfigurable Fabrics

Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest with the recent rapid increase in both size and speed of FPGAs. One of the major obstacles in the way of wider adoption of (re)configurable computing is the lack of high-level tools that support the efficient mapping of programs expressed in high-level languages (HLL) to reconfigurable fabrics. The major difficulty in such a mapping is the translation from a temporal execution model to a spatial execution model. An intermediate representation (IR) is the central structure around which tools such as compilers and synthesis tools are built. In this paper we propose an IR specifically designed for reconfigurable fabrics: CIRRF (Compiler Intermediate Representation for Reconfigurable Fabrics). We describe the design of CIRRF and its initial implementation as part of the ROCCC compiler for translating C code to VHDL. CIRRF is designed to support the creation of a datapath and the scheduling of operations on it. It provides support for buffers, look-up tables, predication and pipelining in the datapath. One of the important features of CIRRF, and ROCCC, is its support for the import of pre-designed IP cores into the original C source code allowing the user to leverage the huge wealth of existing IP cores while programming the configurable platform using a HLL. Using experiments and examples we show that CIRRF is a solid foundation to generate high-performance hardware.     

一种基于机器描述的VLIW DSP编译技术

VLIW DSP机器由于硬件控制简单,指令的并行性完全在编译时决定,因此编译程序成为基于VLIW DSP机器应用的关键因素。文章描述通过在编译程序中使用目标机器描述技术,提高了编译程序的可重定目标性,减少了生成目标编译程序的难度。     

A Data-Parallel FP Compiler

In data-parallel programming, operations are performed simultaneously on all elements of large data structures. Backus′s FP functional language promotes this view. FP provides a large set of data rearrangement primitives, and a useful set of functional combining forms that are applied to entire data structures. We describe an FP compiler that generates programs capable of exploiting data-parallelism. The FP compiler deduces the type and shape of objects through type inference, and generates efficient parallel implementations of combining forms. In addition, the compiler determines the effects of data rearrangement functions at compile-time, thereby avoiding creation of large intermediate data structures, and reducing interprocessor communication overhead. FP and its compiler are formally specified, reducing ambiguity concerning constructs of the language and results of the compiler. Performance and speed-ups achieved from our compilation and optimization techniques are demonstrated with timings from a prototype implementation on the Connection Machine CM-2.