集成电路单粒子瞬态效应与测试方法

随着器件尺寸的等比例缩小,单粒子瞬态效应对集成电路的影响愈发明显,其产生机理及作用更加复杂。从集成电路单粒子瞬态脉冲的产生机理及模型出发,讨论分析了模拟和数字集成电路的单粒子瞬态效应,介绍了单粒子瞬态脉冲宽度的测试方法与测试结构。     

集成电路单粒子瞬态效应与测试方法

随着器件尺寸的等比例缩小,单粒子瞬态效应对集成电路的影响愈发明显,其产生机理及作用更加复杂。从集成电路单粒子瞬态脉冲的产生机理及模型出发,讨论分析了模拟和数字集成电路的单粒子瞬态效应,介绍了单粒子瞬态脉冲宽度的测试方法与测试结构。     

深亚微米CMOS反相器的单粒子瞬态效应研究

针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。     

一种SRAM型FPGA单粒子效应故障注入方法

随着FPGA在航天领域的广泛应用,SRAM型FPGA的单粒子故障也越来越引起人们的重视,用故障注入技术模拟单粒子效应是研究单粒子效应对SRAM器件影响的重要手段,该文主要研究SRAM型FPGA单粒子翻转、单粒子瞬态脉冲的故障注入技术,并在伴随特性的基础上,提出一种单粒子瞬态脉冲故障注入技术。该方法使注入故障脉冲宽度达到...     

单粒子瞬态效应硬件注入模型实现和仿真

基于量化组合逻辑门延迟思想和扫描测试的方法,提出了一种适用于FPGA硬件模拟单粒子瞬态效应的门级注入模型.该模型考虑了电气掩蔽效应对脉冲传输的影响,通过该模型可以对组合电路任意逻辑门进行错误注入.基于该模型对ISCAS’85基准电路进行单粒子瞬态的研究,实验结果表明该脉冲产生方法高效,注入速度达到105 faults/s.     

脉冲激光试验评估模拟电路单粒子效应

利用脉冲激光对典型模拟电路的单粒子效应进行了试验评估及加固技术试验验证,研究2种不同工艺的运算放大器的单粒子瞬态脉冲(SET)效应,在特定工作条件下两者SET脉冲特征规律及响应阈值分别为79.4 pJ和115.4 pJ,分析了SET脉冲产生和传播特征及对后续数字电路和电源模块系统电路的影响。针对SET效应对系统电路的危害性,设置了合理的滤波电路来完成系统电路级加固,并通过了相关故障注入试验验证,取得了较好的加固效果。     

高速PWM单粒子瞬态效应脉冲激光模拟试验研究

利用脉冲激光验证高速脉宽调制控制器（Pulse Width Modulator,PWM）单粒子瞬态效应的敏感性和防护设计。试验中,通过改变脉冲激光能量,逐步扫描PWM控制器电路,确定了诱发单粒子瞬态效应的激光能量阈值和敏感区域。通过改变PWM控制器软启动配置电路设计,验证了防护电路设计的合理性,为卫星电源子系统的单粒子瞬态效应防护设计提供技术参考。     

PDSOI工艺下单粒子瞬态脉冲宽度分析

单粒子瞬态脉冲宽度是评价电子系统软错误率的重要参数之一。针对0.13 μm、部分耗尽型绝缘体上硅(PDSOI)工艺下的反相器链,解析地计算了反相器中产生的单粒子瞬态脉冲宽度,仿真了产生的单粒子瞬态脉冲在反相器链中传播时的临界脉冲宽度和传输率随级数变化情况。仿真结果表明,单粒子瞬态脉冲宽度的大小在几十皮秒到几百皮秒之间,反相器链的级数对临界脉冲宽度和传输率影响较大。最后仿真得到在输入单粒子瞬态脉冲宽度较小时,建立保持时间与输入脉冲宽度有关。该结果有利于电气掩蔽建模和锁存掩蔽建模准确性的提高。     

65 nm体硅工艺NMOS中单粒子多瞬态效应的研究

针对NMOS场效应晶体管由重离子辐射诱导发生的单粒子多瞬态现象,参考65 nm体硅CMOS的单粒子瞬态效应的试验数据,采用TCAD仿真手段,搭建了65 nm体硅NMOS晶体管的TCAD模型,并进一步对无加固结构、保护环结构、保护漏结构以及保护环加保护漏结构的抗单粒子瞬态效应的机理和能力进行仿真分析。结果表明,NMOS器件的源结和保护环结构的抗单粒子多瞬态效应的效果更加明显。     

SiGeBiCMOS线性器件脉冲激光单粒子瞬态效应研究

验证SiGe BiCMOS工艺线性器件的单粒子瞬态（Single Event Transient,SET）效应敏感性,选取典型运算放大器THS4304和稳压器TPS760进行了脉冲激光试验研究。试验中,通过能量逐渐逼近方法确定了其诱发SET效应的激光阈值能量,并通过逐点扫描的办法分析了器件内部单粒子效应敏感区域,并在此基础上分析了脉冲激光能量与SET脉冲的相互关系,获得了单粒子效应截面,为SiGe BiCMOS工艺器件在卫星电子系统的筛选应用以及抗辐射加固设计提供数据参考。     

Reliability for nanomagnetic logic (NML) readout circuit under single event effect

In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.     

基于锎源的N沟道VDMOS器件单粒子效应研究

分析了N沟道VDMOS器件的单粒子辐射损伤机理和损伤模式,讨论了VDMOS器件的单粒子辐射加固措施。使用锎源,对采取了加固措施的一款200 V高压N沟道VDMOS器件进行单粒子效应试验研究。对比分析了不同漏源电压和栅源电压以及不同真空度对VDMOS单粒子效应的影响,可为VDMOS器件的单粒子辐射加固、试验验证及应用提供参考。     

功率VDMOSFET单粒子效应研究

阐述了空间辐射环境下n沟功率VDMOSFET发生单粒子栅穿(SEGR)和单粒子烧毁(SEB)的物理机理。研究了多层缓冲局部屏蔽抗单粒子辐射的功率VDMOSFET新结构及相应硅栅制作新工艺。通过对所研制的漏源击穿电压分别为65V和112V两种n沟功率VDMOS-FET器件样品进行锎源252Cf单粒子模拟辐射实验,研究了新技术VDMOSFET的单粒子辐射敏感性。实验结果表明,两种器件样品在锎源单粒子模拟辐射实验中的漏源安全电压分别达到61V和110V,验证了新结构和新工艺在提高功率VDMOSFET抗单粒子效应方面的有效性。     

星载环境下可重构技术分析

针对卫星在宇宙空间运行易受到各种高能粒子辐射,产生的单粒子现象会影响卫星正常工作的问题,通过总结传统的抗单粒子效应的几种方法、可重构技术的发展与分类,分析研究了星载可重构系统设计方法用来抗空间环境辐射效应。通过硬件平台的动态重构可以有效克服单粒子效应的影响,实现远程故障维修、硬件可升级、可靠性提高和成本降低等目标。     

Modeling single event crosstalk speedup in nanometer technologies

With advances in CMOS technology, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. In addition, coupling effects among interconnects can cause SE transients to spread electronically unrelated circuit paths which may increase the SE Susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work reports on the signal speedup effects caused by SE crosstalk and then proposes a best-case delay estimation methodology for use in design automation tools for the first time to our knowledge. The SE coupling speedup expressions derived show very good results in comparison to HSPICE results. Results show an average error of about 8.42% for best-case delay while allowing for very fast analysis in comparison to HSPICE.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

Experimental study on the single event effects in pulse width modulators by laser testing

This paper presents single event effect (SEE) characteristics of UC1845AJ pulse width modulators (PWMs) by laser testing. In combination with analysis to map PWM circuitry in the microchip dies, the typical SEE response waveforms for laser pulses located in different circuit blocks of UC1845AJ are obtained and the SEE mechanisms are analyzed. The laser SEE test results show that there are some differences in the SEE mechanisms of different circuit blocks, and phase shifts or changes in the duty cycles of few output pulses are the main SEE behaviors for UC1845AJ. In addition, a new SEE behavior which manifests as changes in the duty cycles of many output pulses is revealed. This means that an SEE hardened design should be considered.     

Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm²; (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.     

锗硅异质结双极器件单粒子效应与加固技术研究进展

锗硅异质结双极晶体管(Silicon-Germanium Heterojunction Bipolar Transistors, SiGe HBT)具有高速、高增益、低噪声、易集成等多种优势,广泛应用于高性能模拟与混合信号集成电路。同时,基区能带工程带来的优异低温特性以及良好的抗总剂量、抗位移损伤能力使其拥有巨大的空间极端环境应用潜力。然而,SiGe HBT固有的器件结构使其对单粒子效应极为敏感,并严重制约了SiGe电路综合抗辐射能力的提升。针对上述问题,综述了SiGe HBT单粒子效应及加固技术的研究进展,详细阐述了SiGe HBT单粒子效应的基本原理,分析了影响单粒子效应敏感性的关键因素,并对比了典型加固方法取得的效果,从而为抗辐射SiGe工艺开发和电路设计提供参考。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。