低压低功耗模拟集成电路设计技术及展望

低压、低功耗模拟集成电路设计受到多种因素的制约。围绕这些制约因素,回顾了国内外在模拟集成电路低压、低功耗设计领域的方法和技术的发展现状,主要涉及:轨对轨设计技术、亚阈值工作区技术、阈值电压降低技术、组合晶体管技术、横向BJT技术、SOI技术等。分析并比较了各种设计方法的优劣;并对模拟电路低压低功耗设计技术的发展趋势进行了展望。     

降低阈值电压的方法

MOSIC 比双极集成电路需要的电源电压高,双极 IC 的阈值电压约0.7伏,以前的MOS 的阈值电压就需3伏。互补型 MOS 阈值电压若近似3伏,就需要近6伏的电源电压,若要以1.5—3.0伏低电源电压驱动时,其阈值电压就必须近0.5—1.0伏,     

考虑弛豫效应的SiC MOSFET阈值电压测量方法研究

碳化硅(SiC) MOSFET栅极氧化层中的陷阱造就了其独特的阈值电压弛豫效应的特性，使得SiC MOSFET的阈值电压定义和测量成为一个棘手的问题。首先基于弛豫效应的饱和现象，提出了“预偏置+测量”组合的测量方法，一共需要测量两次阈值电压，以确定阈值电压漂移的上下限，并以其平均值定义为阈值电压。然后设计实验测量电路，对某型号SiC MOSFET器件在不同预偏置条件下进行实验测量，分析预偏置电压和脉冲持续时间对测量结果的影响，结果表明合理选择预偏置阶段的实验条件可以确保弛豫效应达到饱和，并可得到重复性的阈值电压测量结果。     

SiC MOSFET偏压温度不稳定性阈值电压测试方法研究

SiC MOSFET阈值电压漂移问题是器件可靠性面临的主要挑战,阈值电压测量的准确性对于评估器件在偏压与温度应力下的阈值电压稳定性极为重要。围绕偏压与温度应力下SiC MOSFET阈值电压测试的问题,分析SiC MOSFET阈值电压漂移特性的影响因素,介绍国外偏压温度不稳定性评估标准的现状,对标准中所有测试方法均进行详细分析,分类归纳总结现有测试方法,分析各类测试方法的优缺点。     

近阈值低功耗8位微处理器的设计与实现

随着RFID、可穿戴设备和物联网等应用的兴起,低吞吐率、功耗和能耗敏感的芯片设计开始受到广泛的关注,基于阈值电压的低功耗电路设计成为新的发展方向。文中基于SMIC0.13μm1P6M混合信号工艺,通过设计面向近阈值电压的标准逻辑库,在采用标准Top-Down设计流程的基础上,完成了一款近阈值低功耗8位微处理器的设计。封装后芯片的测试结果表明,该微处理器的最低工作电压可达0.2V,工作频率1k Hz~25MHz。与基于传统逻辑库的微处理器比,在20MHz的工作频率下,功耗降低了36%。     

应变SiGe沟道PMOSFET阈值电压模型

首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。     

AMOLED驱动管阈值的补偿方法综述

有机电致发光二极管(Organic Light Emitting Diode,OLED)在显示技术中得到越来越广泛的应用,特别是AMOLED已经成为新一代显示技术发展方向,但是一系列影响AMOLED显示质量和寿命的问题需要得到解决。其中,AMOLED的驱动TFT的阈值电压偏移严重影响了AMOLED的性能。该文综述了当前几种典型的AMOLED的像素驱动结构及其驱动TFT阈值电压的补偿方法,并详细介绍其补偿原理。     

OLED抑制阈值电压漂移像素电路分析

OLED像素电路存在驱动晶体管阈值电压漂移的问题,引起显示效果的下降.在专利数据库中进行检索和分析,对韩国三星近年来提出的多种用于抑制驱动晶体管阈值电压漂移的OLED像素电路的原理进行了分析,并提出了一些设计方面的考虑因素.     

快闪存储器阈值电压分布读取和修正方法

在快闪存储器中,多晶硅浮栅的漏电、存储单元之间的干扰、长期的编程擦除操作都会使存储单元的阈值电压发生漂移,使采用多电平技术的快闪存储器的阈值电压分布规划变得越来越困难。针对这一问题,提出了一种快闪存储器阈值电压分布读取方法,该方法能准确地测量快闪存储器的阈值电压分布,给快闪存储器阈值电压分布规划和编程擦除算法的设计提供参考。     

FPGA的静态功耗分析与降低技术

FPGA已经被广泛用于实现大规模的数字电路和系统,随着CMOS工艺发展到深亚微米,芯片的静态功耗已成为关键挑战之一。文章首先对FPGA的结构和静态功耗在FPGA中的分布进行了介绍。接下来提出了晶体管的漏电流模型,并且重点对FPGA中漏电流单元亚阈值漏电流和栅漏电流进行了详细的分析。最后根据FPGA的特点采用双阈值电压晶体管,关键路径上的晶体管采用低阈值电压栅的晶体管,非关键路径上的晶体管采用高阈值电压栅的晶体管,以此来降低芯片的静态功耗。     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

一种电机驱动芯片的欠压保护电路设计

基于先进的0.35um BCD工艺,对传统欠压保护电路缺点进行分析,设计实现了一种可应用于电机驱动芯片的欠压保护电路。电路结构简单,不需要额外的带隙基准电路,同时也省去了电压比较器电路。特别地,电路考虑了器件的温度特性,减少温度变化对电路的翻转阈值和迟滞量的影响。通过使用Cadence Spectre工具进行电路仿真,结果表明电路工作正常,当电源电压降低到2.7V时,输出低电平,当电压重新上升到2.83V时,输出恢复到高电平,迟滞量为0.13V,具有迟滞功能。     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

一种高精度快速响应欠压锁定电路设计

针对传统欠压锁定(UVLO)电路结构复杂和响应速度慢的问题,设计了一种高精度的快速响应欠压锁定电路.该电路整体均由CMOS管组成,结构简单且易于实现.采用电流模控制技术,随电源电压呈二次方曲线变化的自偏置电流控制阈值电压的产生,有效提高了电路的响应速度.该欠压锁定电路基于0.18μm BCD工艺设计,并利用HSPICE进行仿真验证,当电源电压在0～5V区间变化时,输出电压翻转的上阈值门限为3.91 V,相应下阈值门限为3.82V,迟滞量为90 mV,温度在-40～125℃范围变化时,阈值门限电压容差仅为0.9μV,可实现输出电压的高精度转换,电路面积仅为15 μm×48μm.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

低压CMOS带隙电压基准源设计

在对传统典型CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈技术,提出了一种1-ppm/°C低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路设计。放大器输出用作电路中PMOS电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC0.35μmCMOS工艺实现,采用HSPICE进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

一种用于AC/DC控制器中电压基准源的设计

提出了一种新颖的可用于AC/DC控制芯片中的基准电压源电路。此电路以PTAT（proportional to absolutetemperature）电流为偏置电流,利用二极管连接的MOS晶体管迁移率和阈值电压的温度系数可相互补偿的特性,产生与温度无关的栅源电压。该电路结构简单,既无启动电路也无运放,避免了运放失调对基准源的影响,设计采用CSMC0.5μm BCD工艺。仿真结果表明,该基准电压源具有较低的温度系数和高电源电压抑制比,可作为AC/DC控制芯片中迟滞比较器的参考源。     

Technology challenges for integration near and below 0.1 μm

Technology challenges for silicon integrated circuits with a design rule of 0.1 μm and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 μm currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 μm which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 μm technology. 0.1 μm technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 μm are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 μm are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 μm is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.