2.5G和3G蜂窝基站用全集成上、下变频混频器

Maxim Integrated Products公司开发出一种用于2.5G和3G蜂窝基站的含片上本振(LO)开关和缓冲级的全集成上、下变频无源SiGe混频器(型号MAX2031)。该器件的输入三阶截取点(IIP3)为36dBm,1dB交调产物(IP1dB)27dBm,噪声系数(NF)7dB,变频损耗仅7dB。此外,上述MAX2031的二阶和三阶乱真抑制优良。该器件所提供的中频范围特宽,为dc—250MHz,LO注频范围为960MHz—1180MHz。上述片上集成SPDT LO(单刀双掷本振)开关确保频率跳动,该开关的开关速度小于50ns,LO1—LO2隔离为49dB。电路板的驱动功率为0dBm,LO缓冲级提供±3dB的驱动变…     

用频谱仪以及信号源实现快速扫频测试

本文主要介绍了Agilent信号分析仪的最新选件ESC,以及ESC是如何应用在快速扫频测试中。最后还比较了频谱仪跟踪源选件和频谱仪ESC选件之间的区别。     

无线基站时钟链路杂散指标优化

文章对LO本振杂散指标要求进行了分析,以及对链路上各节点的提出了指标要求。首先介绍了RRU EVM指标要求,以及EVM指标到LO本振的相噪和杂散的分解。其次,对锁相环特性进行了分析,公式推导计算,并测试了链路上各节点的频率响应特性。最后,根据测试情况以及链路上节点环路带宽设计进行了总结,提出了各节点需要到达的指标要求。通过文章的分析,对PLL整个链路杂散传递有更深入的认识,为各节点环路带宽设计提供规范,为分析LO本振杂散来源提供参考。     

基于DSP的微波信号源控制

为了实现信号源的小型化,便携性,采用DSP芯片TMS320LF2407A利用具有脉宽调制（PWM）功能的引脚,根据芯片资料中控制信号的数学关系式和时钟关系,编程实现输出3路同步时钟控制信号CLOCK,DATA,LE控制AD公司频率合成芯片ADF4156的方法来控制微波信号源的点频扫频等动作。做了示波器测试控制信号,频谱仪测试信号源实验,可以清晰地看到控制信号在时域上的对应关系以及频谱仪中所设置频率信号的功率以及信号在整个频段的移动过程。结果表明输出的控制信号能够精确地使信号源实现点频和扫频功能,具有控制时钟,扫频速度可调,按键控制灵活的特点。     

扩频通信系统中一种实现数字下变频器的算法

介绍了在扩频通信系统中一种产生数字下变频器(DDC)正交本振信号的方法--CORDIC算法,它在产生正弦值和余弦值时不需要太多的ROM资源,只需要简单的移位和加法等迭代操作,很容易在VLSI芯片上实现;文中也给出了用该算法实现DDC的VLSI结构.     

目黑MCM-7000型集中扫频信号源的双基线改制

目黑MCS-7000型集中扫频信号源,主要用来调试全波段无线电广播接收机的中频电路,中波、短波、调频等波段的中频特性和频率复盖及跟踪等。一般收录机均为多波段,且SW2多采用SW1本振的二次谐波作本振。这样使每个工位的工作量不能均匀划分,给工艺安排造成困难,且由于分波段调试,所以调试三波段的收录机,要分三个工位,麻烦费时。本文介绍将该集中扫频信号源改制为双基线方式,即将MW与SW信号合在一起输出,直接将0.5～30MHz扫频信号显示在屏幕双基线上。这样原全波段AM-FM的收录机要分四个工位调试,现只要三个工位调试即可完成。提高了劳动效率30％,减轻了工人劳动强度。     

电视发射机图象网纹的产生与排除

我台使用北广产三频道10KW发射机,在使用和维护设备时,经常遇到高频网纹和低频50Hz场频干扰图象问题,严重影响了收看效果。本文就这些问题的产生及排除方法在此进行探讨。1本振倍频回路失调造成的高频网纹变频本振倍频回路采用三调谐回路(见图1）。在具体调试当中,首先断开线路,从A端送本频道的本振扫频频率,从B端检波得到直流曲线(见图2),然后将线路接通,送晶振的单频信号,测量本振频率的输出幅度。如果输出偏低,则重新断开线路,送扫频信号重扫“图1”的无源四端网络。如果单频幅度达不到要求,可把检波直流曲线调成两上峰耦…     

电视发射机差转机图像网纹的产生与排除

影响电视播出质量的原因很多,比如在机房监视器的画面上出现高频网纹和低频50Hz场频干扰,它严重地影响了观众收看电视的效果。1本振倍频回路没有调好造成高频网纹北京广播器材厂生产的差转机无论是下变频器还是上变频器,本振倍频回路均采用三调谐回路（见图1）。在具体调试当中,断开线路从A端送本频道的本振扫频频率,从B端检波得出直流曲线如图2。然后,把线路接通,送晶振的单频测量本振频率的输出幅度,如果输出偏低,重新断开线路送扫频信号重扫图1的无源四端网络,如果单频幅度达不到要求,可把检波直流曲线调成两个峰耦合,把第…     

基于ADF4113的本振扫频源的设计与实现

运用数字锁相频率合成的思想,以AD I公司生产的数字分频器和鉴相器ADF4113为核心,设计了频率范围在1.58 GHz~1.78 GHz的本振扫频源。重点阐述了系统的硬件实现,包括系统设计方案、主要电路单元设计以及系统测试结果等,并对该系统在实际调试过程中常见的问题进行了详细的分析。     

YTO驱动电路设计及优化

介绍了现代频谱分析仪中YTO驱动电路的设计和优化。现代频谱分析仪普遍采用FFT分析和扫描分析相结合的方式,YTO通常作为频谱分析仪的扫频本振。该驱动电路利用带反馈的开关切换电路,不但满足FFT分析时的低相噪要求,同时满足扫频分析时的扫描速度要求。该电路已成功应用在频谱分析仪中。     

基于DDS的本振扫描电路设计

介绍了频谱分析仪中本振自动扫描的几种常用工作方式,给出了利用DDS来实现本振自动扫描的原理方法。论述了在实际工程中如何应用FPGA设计来实现本振的自动扫描,并给出了设计主要指标结果。     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

Design and measurement of a 53 GHz balanced Colpitts oscillator

A 53 GHz Colpitts oscillator implemented in a SiGe:C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer down-converted the oscillating frequency to an intermediate frequency (IF) below 26.5 GHz. By adjusting the local os-cillating (LO) frequency and recording the changes of IF frequency, the oscillator's output frequency (RF) was determined. Additionally, using phase noise theory of mixers, the oscillator's phase noise was estimated as-58 dBc/Hz at 1 MHz offset and the output power was about-21 dBm. The chip is 270×480 μm in size.     

An LO architecture with novel wide locking range,quadrature output RILFDs and ILROs for cognitive radio applications

In this paper, a wide locking range, quadrature output ring type injection locked frequency divider (ILFD) is presented for division ratios of 3 and 4. This ILFD proposes a novel injection scheme that shapes the injection signal to a proper form and provides a convenient situation for divider locking. Furthermore, two new wide locking range, low power consumption, injection locked ring oscillators (ILROs) are proposed for quadrature generation in local oscillator architectures. A novel cognitive radio quadrature local oscillator (LO) architecture is presented by utilizing the proposed ILFDs and ILROs to verify the effectiveness of the proposed circuits. Moreover, a new technique is implemented on the LO architecture to widen the frequency range without consuming any extra power. Because of using a single LC tank, this architecture is very compact. Also, it has the benefit of low power consumption and low output phase noise.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

一种高线性无源双平衡混频器

设计了一种适用于1.0～2.0 GHz的高线性下变频混频器。电路设计采用了无源双平衡结构,片内集成宽带巴伦、限幅本振放大器、混频核和偏置电路。为了提高混频器的线性度,在对无源双平衡的结构进行分析的基础上,折中选择混频核的晶体管尺寸,并优化了本振放大器输出信号的幅值及上升时间。基于0.35μm BiCMOS工艺进行了设计仿真,芯片面积为0.9 mm×1.8 mm。流片测试结果表明:射频频率1.0～2.0 GHz,对应本振频率1.0～2.0 GHz,最佳本振输入功率为0 dBm,转换增益大于-7.0 dB,射频输入三阶交调大于25 dBm,混频器工作电压为3.3 V,功耗为112 mW。该高线性无源双平衡混频器可满足工程应用。     

A comparison of planar doped barrier diode performance versusSchottky diode performance in a single balanced, MIC mixer with low LOdrive

This paper demonstrates that an unbiased GaAs planar doped barrier (PDB) diode, single balanced, Ku-band mixer achieves conversion loss performance comparable to a bias-optimized GaAs Schottky design at low local oscillator (LO) power levels for identical RF circuits. An experimental, side-by-side, performance comparison as a function of LO power is presented along with a harmonic balance (HB) simulation. The PDB diode is of interest for its zero-bias requirement and the high pulsed peak power handling potential for low-cost radars     

Design of Lange-couplers and single-sideband mixers usingmicromachining techniques

This paper reports on the design and performance of micromachined Lange-couplers and single-sideband mixers (SSB) on thin dielectric membranes at Ku-band. The micromachined Lange-coupler results in a 3.6±0.8 dB coupling bandwidth from 6.5 to 20 GHz. The Lange-coupler and an interdigital filter are used in a 17-GHz SSB. The SSB mixer requires 1-2 mW of local oscillator (LO) power without dc bias and achieves a 30 dB upper-sideband (USB) image rejection for an IF frequency of 1 GHz and above. The micromachined membrane technology can be easily scaled to millimeter-wave monolithic microwave integrated circuits (MMIC's) to meet the low-cost requirements in automotive or portable communication systems     

Integrated antenna with direct conversion circuitry for broad-band millimeter-wave communications

A compact integrated antenna with direct quadrature conversion circuitry for broad-band millimeter-wave communications is proposed. The conversion circuits include two even-harmonic mixers based on antiparallel diode pairs (APDPs). The equivalent circuit of the APDP derived here provides good agreement with the measured data from 17 to 23 GHz. Overall phase and amplitude imbalance between the in-phase/quadrature (I/Q) output channels are less than 1.2/spl deg/ and 1 dB at IFs of 10 and 100 MHz, respectively. An overall RF power conversion loss of 14.6 dB at the quadrature I/Q channels including the antenna is achieved in the frequency range from 39.75 to 40.25 GHz with a local oscillator (LO) power level of 11.8 dBm. LO leakages at 20 and 40 GHz are -31.5 and -44.8 dBm, respectively. In order to demonstrate the system capabilities for broad-band digital communication, a communication link is built with a pair of the proposed front-ends. Data transmission up to 1 Gb/s data rate for quadrature phase-shift keying modulation is demonstrated.     

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.