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随着集成电路深亚微米制造技术和设计技术迅速发展,系统芯片(SOC)作为一种解决方案得到了越来越广泛的应用。SOC的测试中,内建自测试(Built.In Self-Test,BIST)成为人们研究的热点。文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。 相似文献
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介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求. 相似文献
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《中国无线电电子学文摘》2005,(2)
TN4 2005020497 运动视觉处理5 OC可测性设计与实现/张弘,杨莉,李玉山(西安电 子科技大学)11电子测量与仪器学报一2 004,18(2)一20一24 在设计运动视觉处理5 OC时,文中采用了基于IP的结构,虽然有设计 方法先进、可复用等优点,但也使得SOC复杂性增加,也加大了系统芯 片内部的数据通路完整性、IP和处理器等的测试难度.文中采用了基于 IEEE P1500的测试框架结构以及BIST方法对此SOC以及其中的 IP进行可测性设计的方法,有效地改善了整个SOC测试性能提高了 5 OC的可靠性.仿真试验的结果说明了其测试的有效性.图4参6(刚) 动态范围(S… 相似文献
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一款雷达信号处理SOC芯片的存储器内建自测试设计 总被引:1,自引:1,他引:1
内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障. 相似文献
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缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法. 相似文献
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For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs. 相似文献
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Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%. 相似文献
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Gundolf Kiefer Harald Vranken Erik Jan Marinissen Hans-Joachim Wunderlich 《Journal of Electronic Testing》2001,17(3-4):351-362
We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized. 相似文献
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针对FPGA的逻辑资源测试,提出了一种内建自测试方法.测试中逻辑资源划分为不同功能器件,对应各个功能器件设计了相应的BIST测试模板.在此基础上进一步利用FPGA的部分重配置性能优化BIST测试过程,最终在统一的BIST测试框架下,采用相对较少的配置次数完成了逻辑资源固定故障的全覆盖测试. 相似文献
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Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation. 相似文献
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一种新的低功耗BIST测试生成器设计 总被引:3,自引:1,他引:2
文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值. 相似文献
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This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution. 相似文献
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Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults. 相似文献
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Hua-Guo Liang Sybille Hellebrand Hans-Joachim Wunderlich 《Journal of Electronic Testing》2002,18(2):159-170
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility. 相似文献