Correlating mobility with social encounters: distributed localization in sparse mobile networks

Wireless Networks - Most existing connectivity-based localization algorithms require high node density which is unavailable in many large-scale sparse mobile networks. By analyzing large datasets...     

Hole and electron mobility enhancement in strained SiGe verticalMOSFETs

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions     

Averaged hole mobility model of biaxially strained Si

We aim to establish a model of the averaged hole mobility of strained Si grown on（001）,（101）,and （111） relaxed Si_1-xGe_x substrates.The results obtained from our calculation show that their hole mobility values corresponding to strained Si（001）,（101） and（111） increase by at most about three,two and one times,respectively, in comparison with the unstrained Si.The results can provide a valuable reference to the understanding and design of strained Si-based device physics.     

Electron and hole mobility enhancement in strained SOI by waferbonding

N- and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates     

Hole mobility enhancement and Si cap optimization in nanoscale strained Si1−xGex PMOSFETs

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si_1−xGe_x/Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si_1−xGe_x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length (L_G) Si_0.9Ge_0.1 PMOSFETs with SiO₂ gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si_1−xGe_x devices with L_G=70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.     

Low-field mobility and carrier transport mechanism transition in nanoscale MOSFETs

This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ0) and the low-field mean free path (λ0), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ0 is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ0 is nearly a constant, and λ0 can be used as the "entry criterion" to determine whether the device begins to operate under quasi-ballistic transport to some extent.     

纳米尺度MOSFETs中低场迁移率及输运机理质变研究

本文利用流量散射方法研究了纳米尺度MOSFETs中载流子的输运特性,重点分析了低场迁移率和输运机理质变。针对不同器件结构的MOSFETs,我们给出了一个相同的闭合形式的低场迁移率表达式,它对于漂移扩散输运和准弹道输运都是有效的。基于实验测试结果,我们首先提取了长沟低场迁移率和低场平均自由程,进而从实验和理论上分析了载流子输运机理质变。我们发现,尽管MOSFET中迁移率随沟长缩小而降低,但是低场平均自由程几乎是个常量,它可以作为器件是否实现准弹道输运的尺度判据,并有效地表征载流子的输运机理从漂移扩散输运向准弹道输运的质变。     

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

This letter presents the first experimental study of the mobility in 50-nm gate length (L/sub G/) pMOSFETs highly strained by a contact etch stop layer. Thanks to an advanced characterization method, the mobility is in-depth studied versus the inversion charge density, the gate length and the temperature. The physical origin of the more than 50% mobility enhancement at L/sub G/=50 nm is proven to be the low effective mass of the top valence band rather than any scattering modification. This mobility gain is maintained even at high effective field. This explains the 30% I/sub ON/ enhancement at 50-nm gate length, which is among the best results at such a dimension.     

Characterising gate dielectrics in high mobility devices using novel nanoscale techniques

Strained Si and strained SiGe layers can increase the speed of MOS devices through enhanced electron and hole mobilities compared with bulk Si. However, epitaxial growth of strained Si and SiGe layers induces surface roughness which impacts gate dielectric properties including leakage, breakdown and interface traps. Gate dielectric quality is conventionally studied at a macroscopic level on individual transistors or capacitors. To understand precisely the effect of roughness on the quality and reliability of dielectrics on high mobility substrate devices requires high spatial resolution characterisation techniques. Device processing modifies the dielectric/semiconductor interface compared with its initial form. Therefore nanoscale analysis on completed devices is necessary. In this work, we present new techniques to enable gate leakage analysis on a nanoscale in fully processed high mobility MOSFETs. This is achieved by careful selective removal of the gate from the dielectric followed by C-AFM measurements on the dielectric surface. Raman spectroscopy, AFM and SEM (EDX) confirmed complete layer removal. The techniques are applied to strained Si devices which have different surface morphologies and different macroscopic electrical data. Dielectric reliability is also assessed through device stressing.     

Correlating gate sinking and electrical performance of pseudomorphic high electron mobility transistors

Ti interdiffusion from the Ti/Pt/Au gate into the AlGaAs Schottky barrier layer (SBL) of 0.25-μm GaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) has been studied using the accelerated life testing technique. Based on measurements and modeling, analytical expressions for quantitative correlation between the positive pinch-off voltage (V_P) shift as well as the saturation drain current (I_Dsat) decrease and the physical damage occurring during gate sinking has been developed. It is suggested that the main cause for device failure is the growth of the TiAs phase leading to the decrease in the SBL thickness. Additionally, it is suggested that V_P may be used as a better indicator for device degradation than I_Dsat since it is linearly proportional to the degrading physical characteristic – the Schottky barrier layer thickness.     

Suppression of drain-current overshoot in SOI-MOSFETs using anultrathin SOI substrate

An n-channel SOI-MOSFET fabricated on a very thin (500 Å) SOI substrate exhibited no detectable drain-current overshoot for various gate turn-on pulses. The reason can be ascribed to the suppression of the floating substrate effect, brought about by the quick decay of excess holes     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

Two-dimensional simulations of drain-current transients in GaAsMESFET's with semi-insulating substrates compensated by deep levels

Drain-current transients of GaAs MESFET's with deep donors “EL2” in the semi-insulating substrate are simulated in the range t=10^-13 to 10² s. It is shown that in the drain step responses, there exists a “quasi-steady state” where the deep donors do not respond to the voltage change and the drain currents become constant temporarily. The drain currents begin to decrease or increase gradually when the deep donors begin to capture or emit electrons, reaching real steady-state values. I-V curves are quite different between the “quasi-steady state” and the steady state. Therefore, the deep donors in the semi-insulating substrate can be causes of drain-current drifts and hysteresis in I-V curves. Effects of introducing a p-buffer layer are also studied. It is concluded that the use of a low acceptor density semi-insulating substrate combined with introducing a p-buffer layer is effective to minimize the unfavorable phenomena and to utilize high performances of GaAs MESFET's     

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.     

Measured In-plane hole drift and hall mobility in heavily-doped strained p-type Si1−xGex

Measured in-plane hole drift and Hall mobilities in heavily boron-doped strained Si_1−xGe_x layers are reported. In the range of boron dopings examined (1.5–2.1 × 10¹⁹ cm⁻³), the drift mobility is seen to increase with increasing germanium fraction. The Hall mobility decreases with increasing germanium fraction. Presented at the 1992 EMC, Boston.     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

A universal electron mobility model of strained Si MOSFETs based on variational wave functions

A new model is proposed to describe the electron mobility enhancement in strained Si MOSFETs inversion layers using the variational wave functions in the triangular potential approximation. Phonon scattering and surface roughness scattering are included in this model and electron mobility enhancements due to the suppression of these two scatterings are accounted for, respectively. A process-dependent interface parameter is introduced to fit with various technologies. Results from the model show good agreement with experiments for different Ge mole fractions and for a wide range of vertical effective field and temperature. The model is very interesting for implementation in conventional device simulators.     

Modeling of enhancement factor of hole mobility for strained silicon under low stress intensity

In order to quantitatively characterize the enhancement of hole mobility of strained silicon under different stress intensity conditions, changes of hole effective mass should be studied. In the paper, strained silicon under in-plane biaxially tensile strain based on (0 0 1) substrate and longitudinal uniaxially compressive strain along 〈1 1 0〉 are investigated thoroughly. By solving the Hamiltonian of valence band using K·P model, we can obtain the relationship of density of state effective mass (m_DOS), conductivity effective mass (m_C) and splitting energy in valence band energy with stress intensity for both biaxially tensile strain and uniaxially compressive strain. For the stress intensity less than 1 GPa, the paper presents the models of enhancement factor of hole mobility under the biaxially tensile strain and uniaxially compressive strain. The results show that biaxially tensile strain of silicon cannot enhance hole mobility under low stress intensity, while uniaxially compressive stress of silicon can enhance hole mobility greatly.     

Lattice mobility of holes in strained and unstrained Si1-xGex alloys

Results of the lattice drift mobility in strained and unstrained SiGe alloys are reported for Ge fractions, 0.0⩽x⩽1.0. The mobilities are calculated using acoustic, optical, and alloy scattering mechanisms. Due to the strain-induced symmetry reduction in the band structure of Si_1-xGe_x, the mobility is found to be a tensor with two distinct components parallel and perpendicular to the growth plane. Assuming that the scattering mechanisms are independent of the strain, the strained mobility increases exponentially with increasing Ge content, for x=0.3