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A CMOS realisation of a current operational amplifier operating under 3 V supply voltage is presented. The proposed implementation provides very high common-mode rejection. Results of HSPICE simulation show a high open loop current gain of 67 dB, a gain-bandwidth product of -100 MHz and a common-mode rejection ratio of 150 dB 相似文献
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采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节.提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围.将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题.该VGA电路采用TSMC 0.18 μm标准工艺设计和流片,测试结果表明,1.2V电源电压下,其下截止频率调节范围为1.3~ 244 Hz,增益为49.2,44.2,39.2 dB,带宽为3.4,3.9,4.4 kHz,消耗电流为3.9 μA,共模抑制比达75.2 dB. 相似文献
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Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-gm rail-to-rail input stages is presented. The design features a less than 5% deviation in gm over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply. 相似文献
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为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入.。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0.13μm的CMOS工艺制程,在0.6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为:功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。 相似文献
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《Solid-State Circuits, IEEE Journal of》1981,16(6):669-676
A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W). 相似文献
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为了解决轨对轨运算放大器输入级跨导随共模输入电压变化的影响,采用实时共模电压监测技术,动态跟踪轨对轨运放输入级的跨导变化,通过对偏置电流的高精度定量补偿,从而实现了对输入级跨导的恒定性控制。基于0.18μm CMOS工艺进行了具体电路的设计实现,结果表明:在电源电压3.3 V、负载电阻100Ω、负载电容1 nF的条件下,运放增益为148 dB、相位裕度为61°、功耗为39.6μW,共模输入范围高达0~3.3 V,输入级跨导变化率仅为2.1%。 相似文献
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Hamid Karrari Hassan Faraji Baghtash Esmaeil Najafi Aghdam 《Analog Integrated Circuits and Signal Processing》2017,90(1):207-216
A two-stage, fully differential amplifier is presented in this work. The proposed amplifier enjoys from an intrinsic common-mode feedback scheme, which eliminates the extra common-mode circuitries that are essential in typical fully differential circuits. Besides, the proposed architecture introduces a left-half-plane zero which can be adjusted to cancel out the dominant pole and thus to extend the structure’s bandwidth. The simulation results with TSMC 180 nm standard CMOS technology shows the 92.2 dB DC gain and 49 MHz gain bandwidth product with 89° of phase margin. The amplifier consumes 0.45 mW from 1.8 V power supply. 相似文献
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L. Quintanilla J. Arias L. Enríquez J. Vicente J. Barbolla D. Vázquez A. Rueda 《Analog Integrated Circuits and Signal Processing》2003,34(3):201-209
A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 m CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 W. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges. 相似文献
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This paper presents an alternative implementation of a chopper-modulated current-mode instrumentation amplifier. The structure provides very low-offset voltage at the output due to chopper modulation and residual offset removal path. The residual offset removal path is based on low-pass filtering using grounded capacitances which provides compact design structure compared to various chopper-modulated instrumentation amplifier designs. Rail-to-rail input common-mode range is possible due to transmission gate-based input chopper switching scheme. The design is made using a 0.35-µm CMOS process with ±1.65 V supply voltage. The area of the amplifier is 234µm × 344 µm, including all the filtering elements. The proposed circuit with residual offset removal path provides less than 1 µV input referred offset voltage. The advantage of the proposed instrumentation amplifier is its large bandwidth, simple design scheme and compact area compared to chopper-modulated voltage mode amplifiers. 相似文献
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在分析传统CMOS宽共模输入级结构基础上,设计了一种新型CMOS电路结构实现超宽共模输入范围(ICMR)的运算放大器。此设计通过提取输入共模电平与参考共模电平比较放大,反馈到输入信号端,使信号在放大前共模电平趋近参考共模电平,可扩大输入共模电平范围,并有利于OP core性能保持稳定。电路采用TSMC 0.13μm CMOS工艺进行设计,利用Cadence仿真,结果表明:在3.3 V电源电压下,输入共模范围为-1.5 V~4.8 V,开环增益为74 dB,单位增益带宽为11.4MHz,相位裕度为74°。 相似文献
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《Solid-State Circuits, IEEE Journal of》1986,21(6):1026-1034
The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology. 相似文献
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为了满足高性能开关电源中集成运放的应用需要,设计了一种结构简单且具有轨对轨输出的运算放大器.该运放基于0.5μm BiCMOS 工艺,采用浮动输出的输入信号适配器(ISAFO),将输入信号放大至差分输入级的工作区域,从而实现了轨对轨的运行.对所设计的运放进行了仿真分析,结果表明在工作电源电压为±0.75 V、外接100 kΩ电阻的条件下,该运放的直流开环增益达到了102 dB,单位增益-带宽为6.35 MHz,相位裕度为62.5°,而功耗仅约为150 μW.所设计的运放具有很宽的共模输入范围及较高的增益,所以特别适用于开关电源的误差放大器、过流、过压和过热保护模块中. 相似文献
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Ivanov V. Zhou J. Filanovsky I. M. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(5):397-401
A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage 相似文献
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Apirak Suadet Varakorn Kasemsuwan 《Analog Integrated Circuits and Signal Processing》2013,74(2):387-398
This paper presents a CMOS inverter-based class-AB pseudo-differential amplifier comprising current-mode common-mode feedback (CMFB). The circuit employs two CMOS inverters and the complementary CMFB consisting of current-mode common-mode (CM) detector and transimpedance amplifier. The circuit has been designed using 0.18 μm CMOS technology and operates at 1 V supply. The simulation results demonstrate rail-to-rail operation with low CM gain (?15 dB). The power dissipation of the circuit is 102.5 μW. 相似文献
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Tarmo Ruotsalainen Juha Kostamovaara Riitta Rankinen 《Analog Integrated Circuits and Signal Processing》1994,5(3):247-256
A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances. 相似文献
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Vlastimir D. Pavlović Srdjan D. Djordjević 《International Journal of Electronics》2013,100(4):331-349
In this article, we propose a novel general structure of a linear symmetric fully differential voltage amplifier with a symmetric output. It is applicable to all sets of complementary component pairs such as BJT, JFET and MOSFET. We demonstrate the superiority of the proposed circuit in comparison with the state-of-the-art solutions. The characteristics are illustrated in both frequency and time domains, and a comparison is given between the proposed amplifier and the traditional differential amplifier with a current mirror as an active load for the same set of complementary components in CMOS equally sized W/L = 150/3 technology. The static voltage transfer characteristic of the proposed amplifier has an extremely small linearity error. The deviation from the linear characteristics is less than 0.018 mV for the amplitude of the output differential voltage of 1 Vpp. The common-mode gain by symmetric output is negligible because the proposed structure is fully symmetric. The simulation results demonstrate the efficiency of the proposed amplifier. 相似文献