A Fully Integrated 0.13- μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer

A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator has reduced both the parasitic magnetic and substrate coupling, allowing single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant reduction in die area was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL passive loop filter to reduce the equivalent VCO tuning gain. This improves PLL noise and spur performance and allows the on-chip integration of the loop filter. The digital low-IF tuner allows the use of a discrete step AGC loop that results in lower noise figure and higher linearity. Automatic signal path gain and bandwidth digital calibration was realized using replica ring oscillators. Tuner specifications include: 90 dB gain range, 10 dB noise figure at max gain, +25dBm IIP3 at min gain, 1.3deg rms integrated phase noise, <-50dBc spurs, 0.5-W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm² die area     

A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-μm CMOS

Super-regeneration is re-examined for its simplicity and power efficiency for low-power, short-range communication. A fully integrated super-regenerative receiver in 0.13-mum CMOS is designed to operate in the 2.4 GHz ISM band. A frequency synthesizer scheme tunes the passband. Successive approximation register (SAR) logic driving a current digital-to-analog converter (DAC) calibrates the quench signal to enhance the selectivity of a Q-enhanced filter and the sensitivity of super-regeneration. A single-chip prototype receiver occupies less than 1 mm², has a turn-on time of 83.6 mus, a channel spacing of 10 MHz, and a sensitivity of -90 dBm. A data rate of 500 kb/s is achieved with a power consumption of 2.8 mW, corresponding to energy consumption of 5.6 nJ per received bit.     

A Multimode Transmitter in 0.13 μm CMOS Using Direct-Digital RF Modulator

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm².     

A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 μm CMOS

A single-chip, dual-band transceiver for CDMA2000 is presented. The design supporting the North American cellular and PCS bands features a complete zero-IF receiver, a direct-conversion transmitter and two fully integrated synthesizers with VCOs. The analog receiver front-end comprises two self-matched wideband LNAs, a highly linear demodulator and a third-order baseband filter. In a test version I/Q ADCs and a digital front-end (DFE) to provide channel and matched filtering are included to demonstrate the performance of a fully integrated analog/digital line-up. Measured maximum SNR values of 23 dB and 25 dB for PCS and Cell bands, respectively, are achieved. The transmitter comprises baseband buffers and filters, an I/Q-modulator and separate output drivers for each band. An analog gain control (AGC) for realization of a dynamic range is implemented and a maximum output power of at a total CDG4 urban current of 34 mA is achieved for the PCS band. Measured ACPR1 and values are and 0.998 for the Cell band and and 0.995 for the PCS band, respectively. The chip is fabricated in a 0.13 RF-CMOS process, occupies a die size of 8.4 and operates with a 2.5 V supply.     

A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology

A 71-80 GHz amplifier using 0.13-mum standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This four-stage cascade thin-film microstrip amplifier achieves the peak gain of 7.0 dB at 75 GHz. The 3-dB frequency bandwidth range is from 71 to 80 GHz. The amplifier demonstrates the highest amplification frequency and smallest chip size among previous published millimeter-wave (MMW) 0.13-mum CMOS amplifiers.     

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 μm CMOS Technology

A 2.5 GHz, 30 mW, 0.03 mm², all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.     

An Integrated Ultra-Wideband Timed Array Receiver in 0.13 μm CMOS Using a Path-Sharing True Time Delay Architecture

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 mum CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported.     

A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10^-12 and a power consumption of 3.5 W.     

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-μm CMOS

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated     

A 46-GHz Direct Wide Modulation Bandwidth ASK Modulator in 0.13-μm CMOS Technology

A 46-GHz direct wide modulation bandwidth amplitude shift keying (ASK) modulator with an embedded voltage controlled oscillator (VCO) is proposed in this letter. This circuit is fabricated using a standard commercial bulk 0.13-mum CMOS technology and exhibits a modulation bandwidth wider than 1 GHz with a chip size of 390 times 480 mum². The recovered time-domain waveform shows a very good eye-pattern opening. To the best of the authors' knowledge, this is the first direct ASK modulator with an embedded VCO in the millimeter-wave regime using CMOS processes.     

A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 μm CMOS

A 15.1 dB gain, 2.1 dB (min.) noise figure low-noise amplifier (LNA) fabricated in 0.13 mum CMOS operates across the entire 3.1-10.6 GHz ultrawideband (UWB). Noise figure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise figure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87mm² IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples     

Miniature Four-Way and Two-Way 24 GHz Wilkinson Power Dividers in 0.13 μm CMOS

This letter presents 24 GHz four-way and two-way miniature Wilkinson power dividers (PDs) in a standard CMOS technology. The chip area is significantly reduced using a lumped-element design, and the effective areas of four-way and two-way Wilkinson dividers are 0.33 times 0.33 mm² and 0.12 times 0.29 mm², respectively. The four-way Wilkinson divider results in an insertion loss <2.4 dB, an input/output return loss better 15.5 dB, and a port-to-port isolation >24.7 dB from 22 to 26 GHz. The two-way Wilkinson divider results in an insertion loss <1.4 dB, an input/output return loss better 8.9 dB, and a port-to-port isolation >14.8 dB from 22 to 26 GHz. To the author's knowledge, this is the first demonstration of 24 GHz four-way Wilkinson PD in a standard CMOS technology.     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency     

A 2.2-μm-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-μm CMOS Process

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.     

A 0.13-μ m CMOS Phase Shifter Using Tunable Positive/Negative Refractive Index Transmission Lines

This letter presents a tunable positive/negative refractive index transmission line (TL) phase shifter utilizing active circuits. It comprises a microstrip TL loaded with series varactors and a shunt monolithic microwave integrated circuit (MMIC) to synthesize a tunable inductor. This implementation increases the phase tuning range and maintains the input and output matching of the phase shifter across the entire phase tuning range, while eliminating the need for bulky passive inductors. The phase shifter is capable of providing both positive and negative phase shifts. The MMIC tunable inductors are fabricated in a 0.13-mum CMOS process and operate from a 1.5-V supply. The phase shifter achieves a phase of -40deg to +34deg at 2.5GHz from a single stage with less than -19dB return loss, and better than 1.1-dB insertion loss at 2.5 GHz. The phase shifter has a 1-GHz bandwidth over which the return loss remains better than 12.1dB     

A 48–860 MHz CMOS Low-IF Direct-Conversion DTV Tuner

A CMOS low-IF direct-conversion digital TV (DTV) tuner needs no off-chip harmonic rejection and image filters to receive both terrestrial and cable TV channels in the 48 to 860 MHz frequency range. Complex in-phase and quadrature (I/Q) poly-phase mixing together with coarse active RF filtering suppresses the third-harmonic mixing by 72 dB, and a digital LMS image correlation algorithm reduces the image leakage by 61 dB. A global AGC scheme keeps the signal level in the down-conversion mixer constant, and warrants the RF front-end linearity with strong blockers. Anti-aliasing and digital channel filters are made digitally programmable so that DTV standards with 6–8 MHz channel bandwidths can be supported. The measured system noise figure is 4–7 dB over the whole TV band. When measured at 500 MHz, the sensitivity is $-$86 dBm with ATSC-T 8-VSB signal, and the MER is 31.5 dB with actual J.83/B 256-QAM signal from a commercial CATV source. The chip implemented in 0.18 $mu{hbox{m}}$ CMOS occupies 5$times {hbox{5 mm}}^{2}$, and consumes 750 mW at 1.8 V.      

A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-μm CMOS

In this paper, a current-to-voltage combiner is proposed to realize a highly linear, balanced noise-cancelling low-noise amplifier (LNA) capable of low-voltage operation. The current-to-voltage combiner, implemented in the load of the amplifier, converts the output currents of the parallel common-gate (CG) and common-source (CS) stages of the LNA to voltages, equalizes the amplitudes of the voltages, and combines the voltages to a single output voltage. Since only a CS stage and passive components are employed to cancel the noise and distortion due to the CG input impedance matching circuit, high linearity is achieved in spite of the low supply voltage of 1.2 V. The LNA achieves a noise figure (NF) of 3.0 dB at 2.1 GHz with an input-referred third-order intercept point (IIP3) of +10.5 dBm while consuming 10.5 mA from a 1.2-V supply. The amplifier is fabricated in 0.13-mum CMOS process.     

A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm² and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply