Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

Performance improvement obtained for thin-film transistorsfabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 μm/10 μm TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated     

Degradation due to electrical stress of poly-Si thin filmtransistors with various LDD lengths

The degradation phenomena of polycrystalline silicon (poly-Si) thin film transistors (TFT's) with various lightly-doped drain (LDD) length have been investigated. It is observed that the threshold voltage shift due to electrical stress varies with LDD length. The threshold voltage shift after 4 hours electrical stress of V_g=V_d =30 V in conventional, 0.5 μm, and 2 μm LDD poly-Si TFT's are about 2.7 V, 5.2 V, and 0.8 V, respectively     

Stability of short-channel P-channel polysilicon thin-filmtransistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (⩽3 μm) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N₂O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 μm show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V_G| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V_G| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes     

Stability of N-channel polysilicon thin-film transistors with ECRplasma thermal gate oxide

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (⩽600°C) TFT's exhibited very a small increase of threshold voltage (ΔV_th<0.3 V) under the stress conditions (V_gs=15 V, V_ds=0 V ~15 V, and stress time=5×10⁴ s). The ΔV_t h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V_gs=V_ds while for the stress at V_gsds, degradation of transconductance was the dominant effect seen     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

Improved stability of short-channel hydrogenated N-channelpolycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide

Stability has been investigated for short-channel hydrogenated n-channel polycrystalline thin-film transistors (poly-Si TFTs) with very thin (12 nm) electron cyclotron resonance (ECR) N₂O-plasma gate oxide. The TFTs show negligible changes in the electrical characteristics after hot-carrier stresses, which is due to the highly reliable interface and gate oxide. The hydrogenated TFTs with 3-μm gate length TFTs exhibit very small degradation (ΔV_th<15 mV) under hot-carrier stresses and Fowler-Nordheim (F-N) stress (ΔV_th=₈₁ mV, ΔGm/Gm=2.2%, ΔS/S=4.7%)     

Gate-overlapped lightly doped drain poly-Si thin-film transistorsfor large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO₂ interlayer     

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 Å) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V_ds=30 V, V_gs=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's     

Bias temperature instability in hydrogenated thin-film transistors

The bias temperature instability is studied in hydrogenated n- and p-channel thin-film MOS transistors (TFT's) fabricated using a low-temperature process compatible with active matrix liquid crystal display application. We observe significant threshold voltage and subthreshold slope degradation under both positive and negative bias stress. The degradation increases with increased hydrogen incorporation and is temperature and electric field activated. The experimental results are explained based on trap creation model which depends on the hydrogen content of the device     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films