Latch-up and image crosstalk suppression by internal gettering [in CMOS]

Internal gettering can be used to reduce crosstalk in imagers and latchup susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for crosstalk reduction obtained in an area imager. The current gain /spl beta/ of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1//spl beta/, in accordance with the theory. A Monte Carlo method was developed to calculate the expected transistor current gain. The calculated /spl beta/s are in excellent agreement with the measured values.     

Latchup model for the parasitic p-n-p-n path in bulk CMOS

The inherent parasitic bipolar transistors and p-n-p-n paths in monolithic CMOS circuits can be undesirably triggered into the low resistance and high current state, i.e., latchup. To ensure the safe operation for the future scaled CMOS circuits, an accurate latchup model is required for design optimization. A modified lumped resistance model has been developed which is shown to accurately predict the latchup characteristics provided the device parameters are accurately measured and reflect those at the latchup state. The model includes the spreading resistance effect in the substrate by a resistor network and it is shown to be critical in the latch-up characterization. Experimental data that supports this model is presented. The reversed layouts in CMOS circuits have been shown to greatly improve the latchup holding current. The dynamic characterization of latchup, caused by voltage overshoot at the input terminals, has also been characterized. It is shown that a minimum turn-on time for the latchup triggering exists and is governed by the base transit time in the lateral transistor with an enhanced diffusion coefficient from the high injection effect.     

CMOS结构中的闩锁效应

本文较为详细地阐述了体硅CMOS结构中的闩锁效应，分析了CMOS结构中的闩锁效应的起因，提取了用于分析闩锁效应的集总组件模型，给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明，只要让CMOS电路工作在安全区，闩锁效应是可以避免的，这可以通过版图设计规则和工艺技术，或者两者相结合的各种措施来实现。本文最后给出了防止闩锁效应的关键设计技术。     

一种Bipolar结构中的闩锁效应

闩锁是集成电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致整个器件失效。文章较为详细地阐述了一种Bipolar结构中常见的闩锁效应,并和常见CMOS结构中的闩锁效应做了对比。分析了该闩锁效应的产生机理,提取了用于分析闩锁效应的等效模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过对这些条件的分析表明,只要让Bipolar结构工作在安全区,此类闩锁效应是可以避免的。这可以通过版图设计和工艺技术来实现。文章最后给出了防止闩锁效应的关键设计技术。     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。文章首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图设计和工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应的关键技术方案。     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图、工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应关键技术方案。     

Pseudo epi-cost reduction approach and a paradigm shift in substrate material

Historically, P/P+ epitaxial wafers have been utilized for CMOS products for more than two decades. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen-free active areas, superior oxide quality, and gettering capability compared to bulk nonepi wafers. The epi wafers, however, are costly. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 20%-25%. Pseudo epi or high-temperature hydrogen anneal is expected to save a significant percentage of start material costs over the epi substrate for logic family products where epi wafers have dominated the market.     

Modeling of substrate leakage currents in a high-voltage CMOS rectifier

In high-voltage (HV) CMOS integrated circuits (ICs), substrate leakage currents are important design considerations as they increase power consumption and the risk of latch-up. In safety critical applications, such as in biomedical implants, the problem is particularly important. Unfortunately, substrate leakage current paths are mainly formed by semiconductor process parasitic components, which are difficult to analyze accurately by SPICE schematic simulations. This paper presents a realistic modeling work about the substrate leakage currents in implantable HV ICs. As a case study, a rectifier prototype has been implemented in a 0.35-μm HV CMOS process. The simulations based on the models show good agreement with measurements on the experimental prototype.     

Interstitial iron concentrations across multicrystalline silicon wafers via photoluminescence imaging

We present high‐resolution images of the lateral distribution of interstitial iron across wafers from various positions along the length of a directionally solidified multicrystalline silicon ingot. Iron images were taken on wafers in the as‐cut state and also after two different phosphorus gettering steps performed at 845°C for 30 min, one with an additional anneal at 600°C for 5 h (referred to as extended gettering). The iron images were obtained by taking calibrated photoluminescence (PL) images of the low injection carrier lifetimes, before and after dissociation of iron–boron pairs via strong illumination. The iron images clearly reveal the internal gettering of iron during ingot cooling to grain boundaries and dislocation clusters, resulting in much lower dissolved iron concentrations at those features. In contrast, the PL images of gettered wafers exhibit a reversed distribution of dissolved iron compared to the as‐cut wafers, in other words, with higher interstitial iron concentrations at the grain boundaries than within the grains, most probably owing to the precipitated iron at the grain boundaries partly dissolving during the high‐temperature gettering process. Phosphorus gettering was found to result in a significant reduction of interstitial iron both inside the grains and at grain boundaries. The extended gettering resulted in a further significant reduction in all parts of the wafers and along all sections of the ingot. Copyright © 2011 John Wiley & Sons, Ltd.     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

Surface induced latchup in VLSI CMOS circuits

Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFET's and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p⁺/p-well and n⁺/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.     

Impact of silicon substrates on leakage currents

Leakage currents of n⁺-p-diodes, made on four different groups of p-type silicon substrates, are investigated at temperatures between 50 and 120°C. At these temperatures, diffusion of thermally generated minority carriers from the bulk is the dominant leakage current mechanism and determines the holding time of dynamic memories. Measurements at these temperatures show that for Czochral-sky-grown wafers (CZ) with a high interstitial oxygen concentration as is used for intrinsic gettering, the leakage current densities are about 1O× higher than for CZ wafers with a low oxygen concentration or floating-zone wafers (FZ), and are about 100× higher than for p-p⁺-epitaxial substrates. Simple analytical formulas explaining these large differences will be presented. Finally a short discussion about the optimum substrate for future high-density memories will be given.     

Origin and Control of Material Defects in Silicon VLSI Technologies: An Overview

Very large-scale integrated circuits impose stringent demands on the quality of silicon wafers required for their fabrication. This paper is an overview of the interrelationships among silicon characteristics, processing, circuit performance, and crystal growth. The relationship between circuit performance and defects in the substrate is described, particularly the effects resulting form the transition from LSI to VLSI. The defect-generation process is then discussed in terms of as-grown silicon characteristics and crystal-growth conditions that control them. The interdependence of material parameters, internal gettering procedures used to reduce the effect of defects on device performance, and resistance to the warpage of silicon wafers is reviewed, with special emphasis on the current and future requirements of bipolar, MOS, and CCD processes.     

Origin and control of material defects in silicon VLSI technologies: An overview

Very-large-scale integrated circuits impose stringent demands on the quality of silicon wafers required for their fabrication. This paper is an overview of the interrelationships among silicon characteristics, processing, circuit performance, and crystal growth. The relationship between circuit performance and defects in the substrate is described, particularly the effects resulting form the transition from LSI to VLSI. The defect-generation process is then discussed in terms of as-grown silicon characteristics and crystal-growth conditions that control them. The interdependence of material parameters, internal gettering procedures used to reduce the effect of defects on device performance, and resistance to the warpage of silicon wafers is reviewed, with special emphasis on the current and future requirements of bipolar, MOS, and CCD processes.     

Process technology for radiation-hardened CMOS integrated circuits

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.     

集成电路闩锁效应测试

CMOS制程是现今集成电路产品所采用的主流制程。闩锁效应(Latch-up)是指CMOS器件中寄生硅控整流器(SCR)被触发导通后,所引发的正反馈过电流现象。过电流的持续增加将使集成电路产品烧毁。闩锁效应已成为CMOS集成电路在实际应用中主要失效的原因之一。在国际上,EIA/JEDEC协会在1997年也制订出了半静态的闩锁效应测量标准,但只作为草案,并没有正式作为标准公布。我们国家在这方面还没有一个统一的测量标准,大家都是在JEDEC标准的指导下进行测量。文章针对目前国际上通行的闩锁效应测试方法作一个简要的介绍和研究。     

A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction

A structure-oriented model has been developed to simulate the actual distribution of majority-carrier current flow paths in the substrate when the parasitic p-n-p-n structure with long-stripe geometry in a CMOS (complementary metal—oxide-semiconductor) circuit is at the latch-up state. Based on this structure-oriented model, the voltage drop across the latch-up path in the substrate can be calculated directly from the structure data. Therefore, the equivalent emitter-base shunting resistance in the substrate can be easily obtained and used to accurately predict the holding current. The two-dimensional numerical simulations have been carried out, based on this structure-oriented model, to obtain the emitter-base shunting resistance associated with the parasitic lateral bipolar transistor in the substrate. The computed substrate shunting resistance and the well emitter-base shunting resistance have been used to calculate the holding current with the help of the measured peak parasitic transistor gains. The predicted holding currents have been found to be in good agreement with the experimental data measured from several p-n-p-n structures, including normal and reversed layouts which are all designed by using the long-stripe geometries. Furthermore, the numerical simulations have been extended to predict the effects of the layout changes of the p-n-p-n structures on the latch-up susceptibility.     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

The impact of trench isolation on latch-up immunity in bulknonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates     

Correlations between CMOS latch-up characteristics and substrate structure parameters

A structure-oriented model based on a simplified two-dimensional numerical analysis has been developed to calculate the substrate spreading resistance of a parasitic SCR latch-up path in a CMOS circuit. This model establishes the correlation between the major latch-up characteristics parameters (holding voltage, holding current and triggering current) and the structure parameters in the substrate. The correlations thus obtained have been used to predict the effects of layout and structural changes in the substrate on the latch-up characteristics through the application of this model. It has been verified that the calculated results are in good agreement with both the experimental results of the fabricated devices and the simulation results based on the exact two-dimensional numerical analysis.