Controlled Topology of Block Copolymer Gate Insulators by Selective Etching of Cylindrical Microdomains in Pentacene Organic Thin Film Transistors

We investigate the effect of surface topology of a block copolymer/neutral surface/SiO₂ trilayered gate insulator on the properties of pentacene organic thin film transistor (OTFT) by the controlled etching of self assembled poly(styrene‐b‐methyl methacrylate) (PS‐b‐PMMA) block copolymer. The rms roughness of the uppermost block copolymer film directly in contact with pentacenes was systematically controlled from 0.27 nm to approximately 12.5 nm by the selective etching of cylindrical PMMA microdomains hexagonally packed and aligned perpendicular to SiO₂ layer with 20 and 38 nm of diameter and periodicity, respectively. Both mobility and On/Off ratio were significantly reduced by more than 3 orders of magnitudes with the film roughness in OTFTs having 60 nm thick pentacene active layer. The poor device performance observed with the etched thin film of block copolymer dielectric is attributed to a defective pentacene active layer and the mixed crystalline structure consisting of thin film and bulk phase arising from the massive nucleation of pentacene preferentially at the edge of each cylindrical etched hole.     

Mechanistic Considerations of Bending‐Strain Effects within Organic Semiconductors on Polymer Dielectrics

The development of organic transistors for flexible electronics requires the understanding of device behavior upon the application of strain. Here, a comprehensive study of the effect of polymer‐dielectric and semiconductor chemical structure on the device performance under applied strain is reported. The systematic change of the polymer dielectric results in the modulation of the effects of strain on the mobility of organic field‐effect transistor devices. A general method is demonstrated to lower the effects of strain in devices by covalent substitution of the dielectric surface. Additionally, the introduction of a hexyl chain at the peripheries of the organic semiconductor structure results in an inversion of the effects of strain on device mobility. This novel behavior may be explained by the capacitative coupling of the surface energy variations during applied strain.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Highly Efficient Charge Transport in a Quasi‐Monolayer Semiconductor on Pure Polymer Dielectric

The study of monolayer organic field‐effect transistors (MOFETs) provides an effective way to investigate the intrinsic charge transport of semiconductors. To date, the research based on organic monolayers on polymeric dielectrics lays far behind that on inorganic dielectrics and the realization of a bulk‐like carrier mobility on pure polymer dielectrics is still a formidable challenge for MOFETs. Herein, a quasi‐monolayer coverage of pentacene film with orthorhombic phase is grown on the poly (amic acid) (PAA) dielectric layer. More significantly, charge density redistribution occurs at the interface between the pentacene and PAA caused by electron transfer from pentacene to the PAA dielectric layer, which is verified by theoretical simulations and experiments. As a consequence, an enhanced hole accumulation layer is formed and pentacene‐based MOFETs on pure polymer dielectrics exhibit bulk‐like carrier mobilities of up to 13.7 cm² V^?1 s^?1 from the saturation region at low V_GS, 9.1 cm² V^?1 s^?1 at high V_GS and 7.6 cm² V^?1 s^?1 from the linear region, which presents one of the best results of previously reported MOFETs so far and indicates that the monolayer semiconductor growing on pure polymer dielectric could produce highly efficient charge transport.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Self‐Assembled,Millimeter‐Sized TIPS‐Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric

Here, a highly crystalline and self‐assembled 6,13‐bis(triisopropylsilylethynyl) pentacene (TIPS‐Pentacene) thin films formed by simple spin‐coating for the fabrication of high‐performance solution‐processed organic field‐effect transistors (OFETs) are reported. Rather than using semiconducting organic small‐molecule–insulating polymer blends for an active layer of an organic transistor, TIPS‐Pentacene organic semiconductor is separately self‐assembled on partially crosslinked poly‐4‐vinylphenol:poly(melamine‐co‐formaldehyde) (PVP:PMF) gate dielectric, which results in a vertically segregated semiconductor‐dielectric film with millimeter‐sized spherulite‐crystalline morphology of TIPS‐Pentacene. The structural and electrical properties of TIPS‐Pentacene/PVP:PMF films have been studied using a combination of polarized optical microscopy, atomic force microscopy, 2D‐grazing incidence wide‐angle X‐ray scattering, and secondary ion mass spectrometry. It is finally demonstrated a high‐performance OFETs with a maximum hole mobility of 3.40 cm² V^?1 s^?1 which is, to the best of our knowledge, one of the highest mobility values for TIPS‐Pentacene OFETs fabricated using a conventional solution process. It is expected that this new deposition method would be applicable to other small molecular semiconductor–curable polymer gate dielectric systems for high‐performance organic electronic applications.     

Modeling Polymer Dielectric/Pentacene Interfaces: On the Role of Electrostatic Energy Disorder on Charge Carrier Mobility

Force‐field and quantum‐chemical calculations are combined to model the packing of pentacene molecules at the atomic level on two polymer dielectric layers (poly(methyl methacrylate) (PMMA) versus polystyrene (PS)) widely used in field‐effect transistors and to assess the impact of electrostatic interactions at the interface on the charge mobility values in the pentacene layers. The results show unambiguously that the electrostatic interactions introduce a significant energetic disorder in the pentacene layer in contact with the polymer chains; a drop in the hole mobility by a factor of 5 is predicted with PS chains while a factor of 60 is obtained for PMMA due to the presence of polar carbonyl groups.     

物理汽相生长并五苯晶体薄膜

用物理汽相沉积法在水平系统中生长有机半导体并五苯晶体薄膜.用10～30毫克的源生长出20～30 mm2大小的适合特性测量和器件制备的晶体薄膜.利用扫描电镜(SEM)、透射电镜(TEM)和X射线衍射仪(XRD)等仪器对并五苯晶体薄膜进行了测试分析.     

Following Chemical Charge Trapping in Pentacene Thin Films by Selective Impurity Doping and Wavelength‐Resolved Electric Force Microscopy

Charge trapping is one of several factors that limit the performance of organic electronic materials, yet even in pentacene, a prototypical small‐molecule semiconductor, the precise chemical nature of charge trapping remains poorly understood. Here the effects of three chemical trap‐precursor candidates are examined by layering thin‐film pentacene transistors with different pentacene defect species. The resulting charge trapping is studied in each device via scanning‐probe electric force microscopy coupled with variable‐wavelength sample illumination. Firstly, it is found that layering with pentacen‐6(13H)‐one (PHO) readily produces uniform charge trapping everywhere in the transistor channel, as expected for an active blanket‐deposited trap‐precursor. However, layering with 6,13‐dihydropentacene (DHP) produces fewer, more‐isolated traps, closely resembling the surface potential distribution in pristine pentacene thin films. Secondly, the rates of trap‐clearing versus illuminating wavelength (trap‐clearing spectra) are measured, revealing enhanced trap‐clearing rates at wavelengths assigned to the absorption of either pentacene or the charged trap species. The trap‐clearing spectrum for the PHO‐layered sample closely resembles the spectrum obtained from pentacene aged in a working transistor, while the trap‐clearing spectrum for the DHP‐layered sample resembles the spectrum observed in pristine pentacene. We conclude that PHO competently creates traps in pentacene that match the expected trap‐clearing spectrum for degraded pentacene, while DHP does not, and that the chemical trap species in aged pentacene is very likely PHO⁺.     

Boosting Direct X‐Ray Detection in Organic Thin Films by Small Molecules Tailoring

The attention focused on the application of organic electronics for the detection of ionizing radiation is rapidly growing among the international scientific community, due to the great potential of organic technology to enable large‐area conformable sensor panels. However, high‐energy photon absorption is challenging as organic materials are constituted of atoms with low atomic numbers. Here it is reported how, by synthesizing new solution‐processable organic molecules derived from 6,13‐bis(triisopropylsilylethynyl)pentacene (TIPS‐pentacene) and 2,8‐difluoro‐5,11‐bis(triethylsilylethynyl)anthradithiophene, with Ge‐substitution in place of the Si atoms to increase the material atomic number, it is possible to boost the X‐ray detection performance of organic thin films on flexible plastic substrates. Bis(triisopropylgermylethynyl)‐pentacene based flexible organic thin film transistors show high electrical performance with higher mobility (0.4 cm² V^?1 s^?1) and enhanced X‐ray sensitivity, up to 9.0 × 10⁵ µC Gy^?1 cm^?3, with respect to TIPS‐pentacene‐based detectors. Moreover, similar results are obtained for 5,11‐bis(triethylgermylethynyl)anthradithiophene devices, confirming that the proposed strategy, that is, increasing the atomic number of organic molecules by chemical tailoring to improve X‐ray sensitivity, can be generalized to organic thin film detectors, combining high X‐ray absorption, mechanical flexibility, and large‐area processing.     

Polyelectrolyte Dielectrics for Flexible Low‐Voltage Organic Thin‐Film Transistors in Highly Sensitive Pressure Sensing

Organic thin‐film transistors (OTFTs) can provide an effective platform to develop flexible pressure sensors in wearable electronics due to their good signal amplification function. However, it is particularly difficult to realize OTFT‐based pressure sensors with both low‐voltage operation and high sensitivity. Here, controllable polyelectrolyte composites based on poly(ethylene glycol) (PEG) and polyacrylic acid (PAA) are developed as a type of high‐capacitance dielectrics for flexible OTFTs and ultrasensitive pressure sensors with sub‐1 V operation. Flexible OTFTs using the PAA:PEG dielectrics show good universality and greatly enhanced electrical performance under a much smaller operating voltage of ?0.7 V than those with a pristine PAA dielectric. The low‐voltage OTFTs also exhibit excellent flexibility and bending stability under various bending radii and long cycles. Flexible OTFT‐based pressure sensors with low‐voltage operation and superhigh sensitivity are demonstrated by using a suspended semiconductor/dielectric/gate structure in combination with the PAA:PEG dielectric. The sensors deliver a record high sensitivity of 452.7 kPa^?1 under a low‐voltage of ?0.7 V, and excellent operating stability over 5000 cycles. The OTFT sensors can be built into a wearable sensor array for spatial pressure mapping, which shows a bright potential in flexible electronics such as wearable devices and smart skins.     

A High‐k Fluorinated P(VDF‐TrFE)‐g‐PMMA Gate Dielectric for High‐Performance Flexible Field‐Effect Transistors

A newly synthesized high‐k polymeric insulator for use as gate dielectric layer for organic field‐effect transistors (OFETs) obtained by grafting poly(methyl methacrylate) (PMMA) in poly(vinylidene fluoride‐trifluoroethylene) (P(VDF‐TrFE)) via atom transfer radical polymerization transfer is reported. This material design concept intents to tune the electrical properties of the gate insulating layer (capacitance, leakage current, breakdown voltage, and operational stability) of the high‐k fluorinated polymer dielectric without a large increase in operating voltage by incorporating an amorphous PMMA as an insulator. By controlling the grafted PMMA percentage, an optimized P(VDF‐TrFE)‐g‐PMMA with 7 mol% grafted PMMA showing reasonably high capacitance (23–30 nF cm^?2) with low voltage operation and negligible current hysteresis is achieved. High‐performance low‐voltage‐operated top‐gate/bottom‐contact OFETs with widely used high mobility polymer semiconductors, poly[[2,5‐bis(2‐octyldodecyl)‐2,3,5,6‐tetrahydro‐3,6‐dioxopyrrolo [3,4‐c]pyrrole‐1,4‐diyl]‐alt‐[[2,2′‐(2,5‐thiophene)bis‐thieno(3,2‐b)thiophene]‐5,5′‐diyl]] (DPPT‐TT), and poly([N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)) are demonstrated here. DPPT‐TT OFETs with P(VDF‐TrFE)‐g‐PMMA gate dielectrics exhibit a reasonably high field‐effect mobility of over 1 cm² V^?1 s^?1 with excellent operational stability.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

Systematic Control of Nucleation Density in Poly(3‐Hexylthiophene) Thin Films

While molecular ordering via crystallization is responsible for many of the impressive optoelectronic properties of thin‐film semiconducting polymer devices, crystalline morphology and its crucial influence on performance remains poorly controlled and is usually studied as a passive result of the conditions imposed by film deposition parameters. A method for systematic control over crystalline morphology in conjugated polymer thin films by very precise control of nucleation density and crystal growth conditions is presented. A precast poly(3‐hexylthiophene) film is first swollen into a solution‐like state in well‐defined vapor pressures of a good solvent, while the physical state of the polymer chains is monitored using in situ UV–vis spectroscopy and ellipsometry. Nucleation density is selected by a controlled deswelling of the film or by a self‐seeding approach using undissolved crystalline aggregates that remain in the swollen film. Nucleation densities ranging successively over many orders of magnitude are achieved, extending into the regime of spherulitic domains 10 to 100 μm in diameter, a length scale highly relevant for typical probes of macroscopic charge transport such as field‐effect transistors. This method is presented as a tool for future systematic study of the structure‐function relation in semicrystalline semiconducting polymers in a broad range of applications.     

Influence of Electric Field on Microstructures of Pentacene Thin‐Films in Field‐Effect Transistors

We report on electric‐field‐induced irreversible structural modifications in pentacene thin films after long‐term operation of organic field‐effect transistor (OFET) devices. Micro‐Raman spectroscopy allows for the analysis of the microstructural modifications of pentacene in the small active channel of OFET during device operation. The results suggest that the herringbone packing of pentacene molecules in a solid film is affected by an external electric field, particularly the source‐to‐drain field that parallels the a–b lattice plane. The analysis of vibrational frequency and Davydov splitting in the Raman spectra reveals a singular behavior suggesting a reduced separation distance between pentacene molecules after long‐term operations and, thus, large intermolecular interactions. These results provide evidence for improved OFET performance after long‐term operation, related to the microstructures of organic semiconductors. It is known that the application of large electric fields alters the semiconductor properties of the material owing to the generation of defects and the trapping of charges. However, we first suggest that large electric fields may alter the molecular geometry and further induce structural phase transitions in the pentacene films. These results provide a basis for understanding the improved electronic properties in test devices after long‐term operations, including enhanced field‐effect mobility, improved on/off current ratio, sharp sub‐threshold swing, and a slower decay rate in the output drain current. In addition, the effects of source‐to‐drain electric field, gate electric field, current and charge carriers, and thermal annealing on the pentacene films during OFET operations are discussed.     

Polymer Field‐Effect Transistors Fabricated by the Sequential Gravure Printing of Polythiophene,Two Insulator Layers,and a Metal Ink Gate

The mass production technique of gravure contact printing is used to fabricate state‐of‐the art polymer field‐effect transistors (FETs). Using plastic substrates with prepatterned indium tin oxide source and drain contacts as required for display applications, four different layers are sequentially gravure‐printed: the semiconductor poly(3‐hexylthiophene‐2,5‐diyl) (P3HT), two insulator layers, and an Ag gate. A crosslinkable insulator and an Ag ink are developed which are both printable and highly robust. Printing in ambient and using this bottom‐contact/top‐gate geometry, an on/off ratio of >10⁴ and a mobility of 0.04 cm² V^?1 s^?1 are achieved. This rivals the best top‐gate polymer FETs fabricated with these materials. Printing using low concentration, low viscosity ink formulations, and different P3HT molecular weights is demonstrated. The printing speed of 40 m min^?1 on a flexible polymer substrate demonstrates that very high‐volume, reel‐to‐reel production of organic electronic devices is possible.     

Vapor Phase Growth of Functional Pentacene Films at Atmospheric Pressure

Compared to traditional vacuum evaporation techniques for small organic molecules, organic vapor phase deposition (OVPD) possesses a extra processing parameter: the pressure of process gas P_ch. Here, the influence of large P_ch variations (from 0.1 mbar to atmospheric pressure) on pentacene thin film growth is explored. OVPD operation at higher P_ch is characterized by lower carrier gas velocities and lower organic diffusivities. These result in an invariance of the material utilization efficiency over the entire pressure span and in an advantageous equilibrium evaporation regime in the source. An increase in P_ch yields rough pentacene layers. Classical nucleation theory is applied to demonstrate how the pressure rise triggers homogeneous nucleation in the gas phase, causing the observed roughening. The use of lower deposition rates, higher dilution flow rates, and higher substrate temperatures result in the suppression of gas phase nucleation and the growth of smooth pentacene films at atmospheric pressure. Using these optimized conditions, state‐of‐the‐art pentacene thin film transistors with saturation mobilities above 0.9 cm²/Vs are reproducibly fabricated. p‐Type circuits are also made and a 19‐stage ring oscillator with a stage delay of 51 μs at a supply voltage of 15 V is demonstrated.     

Ultra‐Smooth and Ultra‐Strong Ion‐Exchanged Glass as Substrates for Organic Electronics

The introduction of new substrate materials into the world of electronics has previously opened up new possibilities for novel applications and device designs. Here, the use of ion‐exchanged sodium aluminosilicate (NAS) glass is presented as a new type of substrate that is not only highly damage resistant, but also allows the fabrication of high performance organic electronic devices. The smoothness of the NAS glass surface enables favorable growth of the semiconductor layer, enabling high charge carrier mobilities for typical organic semiconductors, such as pentacene or C60, and a polymer semiconductor. No degradation of the device performance is observed as a result of ion migration into the active device region, and no compromise in substrate strength due to the processing conditions is made. This work suggests the possibility of new, highly durable electronic devices on glass in large area format.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.