数字集成电路的时序分析

文章对数字集成电路设计中的时序分析作了一个概要的介绍。对于些时序分析算法进行了讨论,同时,指出伪路径是时序分析中的一个重要问题。因此,为了进行有效的时序分析,必须同时考虑电路的逻辑行为和时序行为。     

数字电路教学中的时序分析

时序分析在数字电路的设计中有非常重要的作用.本文对数字电路中时序分析的一些基本概念作了简单介绍.在讲授数字电路课程时,这些基本概念也可以作为对教材中基本内容的一种补充,学生能够对数字电路中的时序分析有一个比较清楚的认识.同时,由于目前许多广泛使用的EDA工具中都大量使用这些基本概念,我们认为,掌握这些基本概念,将会对学生了解EDA工具、完成数字电路实验以及从事具体的工作有较大的帮助.     

复分接中数字化定时处理的参数化验证法

在复分接系统中，如同步数字系列，定时处理占有重要地位。数字化定时处理技术应用于ＡＳＩＣ设计时，传统方法需要的仿真代价太大。作者 定时验证的特殊性，提出了定时处理电路验证的概念。同时利用参数化方法对定时处理进行验证，大大缩短了仿真时间。     

一种数模混合芯片中数字电路的时序收敛方案

在数模混合集成电路中,时钟信号是数据传输的基准,它对芯片能否正常工作起决定性的作用。由于数模混合集成电路的特殊性,在对时钟信号进行时钟树综合时,要对其进行特殊的处理。以串行外设接口及电平移位模块为例,提出了一种针对数模混合芯片中数字电路的时序收敛方案,验证结果表明此方案能够使时序很好地收敛。     

复杂数字电路中的单粒子效应建模综述

单粒子效应产生的软错误是影响航天电子系统可靠性的主要因素之一。对其进行建模是研究单粒子效应机理和电路加固技术的有效方法。介绍了深亚微米及以下工艺中影响模型准确性的几种效应机制,包括脉冲展宽机制、电荷共享机制和重汇聚机制等。重点分析了单粒子瞬态、单粒子翻转的产生模型和单粒子瞬态的传播模型。阐述了基于重离子和脉冲激光的模型验证方法。最后,分析了单粒子效应随特征尺寸的变化趋势,并提出了未来单粒子效应建模技术的发展方向。     

源端射频干扰下CMOS数字电路的时序失效机理

当前CMOS数字芯片设计流程缺少对电路电磁抗扰性的检验。大幅电磁干扰会导致数字电路出现电路失效,但电路失效的原因以及电路失效与幅度和频率等干扰参数的关系尚不清楚。针对这一问题,详细研究了源端射频干扰下CMOS数字电路的工作状态。通过给出失效与干扰参数的关系的基本理论,得到CMOS数字电路在受扰情况下的失效原因。结果表明,时序错误是大幅电磁干扰引起CMOS电路失效的主要原因。电路失效可通过电路路径延时的漂移和抖动来解释,漂移和抖动与电磁干扰的幅度和频率存在特定关系,因此时序失效是可预测的。基本理论所描述的失效规律可作为EDA工具的原理,用于芯片设计早期阶段对电路的抗扰性检验。     

动态电路的混合时序分析方法

 本文基于四事件周期波形模型,提出了一般动态门、LO-CMOS、NTP动态门和N-C²MOS锁存器正确工作的时序约束.将混合时序分析方法应用于动态电路的延时计算,提出了动态门延时测试波形的生成算法,能有效处理多个输入同时翻转对延时的影响.本文的研究成果已在SpiceTime中实现,并且应用于一个32位动态加法器的设计,取得了良好效果,如果不考虑伪路径的影响,求值延时和预充延时的最大误差分别为3.62%和8.26%.     

Solid-State Digital Circuits

A portion of this September, 1968, issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS is devoted to expansions of papers dealing with digital circuits presented at the 1968 International Solid State Circuits Conference. At this year's conference, the discussion of implications of integrated device technology was again a major aspect of contributed and invited papers as well as evening discussions. There was less mention of extreme large-scale integration than at the 1967 conference, with emphasis turning to what has been termed "putting the technology to work" for realization of digital circuits and functions.     

高精度时间测量电路与实现

本文介绍了不同类型的时间测量方法,讨论了实现高精度时间测量所采用的电路与实现技术。通过这些方法可以实现皮秒（ps）级的时间测量,满足不同应用场合的需求。     

关于GPS单星定时提高定时精度的研究

为满足特殊用户或固定站点对高精度定时信息的需求,文中重点研究位置已知情况下基于卡尔曼滤波算法的GPS单颗星定时的方法。理论分析及仿真结果表明：与位置未知时四颗星联合定位／定时方法相比,位置已知情况下单颗星定时的精度优于位置未知时多星联合定位定时的时间精度,同时,利用观测到的多颗GPS卫星分别进行单星定时得到的信息,可进一步提高时间精度。     

单电子数据转换电路

提出了两种新型的由单电子晶体管、MOS管和电容组成的数模转换(ADC)和模数转换(DAC)电路.这种混合ADC和DAC电路可在室温条件下工作且负载能力大,功耗低.对这种混合单电子晶体管和MOS管的ADC和DAC电路进行了仿真,仿真结果表明两种电路能够在室温条件下正常工作.采样频率达到100MHz以上,功耗约为0.1μW.     

单电子数据转换电路

提出了两种新型的由单电子晶体管、MOS管和电容组成的数模转换(ADC)和模数转换(DAC)电路. 这种混合ADC和DAC电路可在室温条件下工作且负载能力大，功耗低. 对这种混合单电子晶体管和MOS管的ADC和DAC电路进行了仿真，仿真结果表明两种电路能够在室温条件下正常工作. 采样频率达到100MHz以上，功耗约为0.1μW.     

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

单电子数据转换电路

提出了两种新型的由单电子晶体管、MOS管和电容组成的数模转换(ADC)和模数转换(DAC)电路.这种混合ADC和DAC电路可在室温条件下工作且负载能力大,功耗低.对这种混合单电子晶体管和MOS管的ADC和DAC电路进行了仿真,仿真结果表明两种电路能够在室温条件下正常工作.采样频率达到100MHz以上,功耗约为0.1μW.     

基于量子元胞自动机的逻辑电路

简述了量子元胞自动机 (QCA)的理论及其逻辑电路的实现方式。每个量子元胞包含两个电子 ,它们通过库仑相互作用与邻近元胞耦合。每个量子元胞上的电荷分布趋于沿两垂直轴的某一轴向分布 ,可以以此来表达二进制信息。用这些量子元胞的阵列来实现各种逻辑门     

基于MCT可逆线路的量子线路近邻化排布

为了实现量子线路线性最近邻（LNN）排布,给出了可逆MCT门的最近邻Toffoli门级联方法.为了解决线路近邻化中额外插入的SWAP门增加量子代价的问题,引入NNTS门减少插入的SWAP门数,并给出了MCT门基于NNTS门的最近邻线路排布.提出了量子线路近邻化排布算法,将多控制MCT门通过交换线路的顺序得到其最近邻线路排布,然后将每个NNTS门替换为其最优的LNN量子线路实现,得到该MCT线路的LNN量子线路,该方法可以减少量子线路的长度和量子代价.通过Benchmark例题测试,并与现有的线路近邻化结果进行比较,所需插入的SWAP门数平均减少42.83%,量子代价平均改善率达14.80%.     

Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variation models to estimate the effect of Process, power supply Voltage, and Temperature (PVT) variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of circuits designed in 65, 45, and 32?nm CMOS technologies are presented demonstrating that the models can be used for the analytical derivation of delay variability windows and delay variability statistical distributions associated to process variations. This information can be used during the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of PVT variations to be assessed in the design environment. On the other hand, it allows boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits’ performance can simultaneously be analyzed with those of power supply voltage and temperature variations. Experimental results have also been obtained on several FPGA boards including nanometer-scale Xilinx? and Altera? devices. These results provide a proof-of-concept, on real circuits, of the practical usefulness of the models.     

Josephson Digital Devices and Circuits

A review of the progress in the field of Josephson digital devices and circuits is presented. Since the first report of measurements on the switching speed of a Josephson junction in 1966, a large variety of circuits have been developed, with one having a delay of only 13 ps. With miniaturization beyond the present 2.5-mu m linewidths, this remarkable speed probably can be exceeded. It is pointed out that the high speed is combined with very low power so that the high packing density needed to make use of the speed is possible. The paper reviews the Josephson junction and its incorporation into logic gates and memory cells. References are given to larger systems using these elements.     

A Digital Cross-Connect System for Digital Data Circuits

The AT&T subrate data cross-connect system (SRDC) brings the capabilities of the digital access and cross-connect system (DACS) used primarily for analog circuits to the digital data world, including the capability of mechanized remote provisioning and maintenance. The SRDC performs DACS-equivalent functions on 64 kbit/s channels of the Digital Data System (DDS) and other similar emerging data networks at the 2.4, 4.8, 9.6, and 56 kbit/s rates. An SRDC-equipped DACS frame can process both voice and digital data in a shared arrangement. It can also provide all the functions necessary for a DDS hub office environment, including subrate multiplexing, multipoint functions, dataport error correction and secondary channel processing. The operational functions supported by SRDC include circuit testing, facility performance monitoring, circuit and equipment provisioning, memory administration, and equipment maintenance.     

硬件描述语言与数字电路教学

以交通灯控制器的设计为例,介绍了ABEL硬件描述语言在 电子设计中的应用 ,并探讨了硬件描述语言对数字电路设计方法的影响及现代数字电路和教学方法。