IGBT准数值模型和模拟

本文采用数值计算与解析模型相结合的方法，建立了ＩＧＢＴ稳态特性的准数值模型。基于此模型与瞬态特性的电荷控制解析模型，我们开发了绝缘栅晶体管（ＩＧＢＴ）的稳态和瞬态准数值模拟软件包ＩＧＴＳＩＭ，可以模拟与ＩＧＢＴ的几何结构、掺杂分布、少于寿命相联系的直流和关断特性．本文介绍模拟所采用的物理模型、模拟技术和得到的结论，并给出部分模拟实例．     

陷阱俘获存储器中电荷积累过程对保持特性的影响

本文通过数值模拟的方法对陷阱俘获存储器单元在多次擦写过程中的电荷积累过程进行了分析。由于多次擦写后陷阱电荷的积累,电荷之间的复合过程成为一个重要的问题。分析结果显示擦写过程中积累的空穴会对存储器的保持特性产生影响,同时在分析器件保持特性的时候电荷之间的复合机制必须加以考虑。     

4H-SiC MESFET结构与直流特性研究

运用二维器件模拟器ISETCAD对4H-SiCMESFET不同结构的直流特性进行了模拟,重点考虑表面陷阱对直流特性的影响。与凹栅结构相比,埋栅结构的器件降低了表面陷阱对电流的影响,饱和漏电流提高了37%,而且阈值电压的绝对值增大、跨导升高,对提高4H-SiCMES-FET器件的输出功率起到一定的作用。     

SiGe HBT大信号扩散电容模型研究

基于SiGe HBT（异质结双极晶体管）大信号等效电路模型,建立了SiGe HBT大信号发射结扩散电容模型和集电结扩散电容模型．该模型从SiGe HBT正反向传输电流出发,研究晶体管内可动载流子所引起的存储电荷（包括正向存储电荷和反向存储电荷）的基础上,同时考虑了厄利效应对载流子输运的影响,其物理意义清晰,拓扑结构简单。将基于大信号扩散电容模型的SiGe HBT模型嵌入PSPICE软件中,实现对SiGe HBT器件与电路的模拟分析。对该模型进行了直流特性模拟分析,直流模拟分析结果与文献报道的结果符合得较好,瞬态特性分析结果表明响应度好。     

双阱CMOS器件单粒子瞬态效应机理研究

介绍了一种65 nm 双阱CMOS工艺设计的六管SRAM单元的抗辐射性能。通过三维有限元数值模拟的方法,分析了SRAM单元的单粒子瞬态效应在NMOS管中的电荷收集过程和瞬态脉冲电流的组成部分,并提出一种高拟合度的临界电荷计算方案。双阱器件共享电荷诱发的寄生双极放大效应对相邻PMOS管的稳定性有着显著的影响,高线性能量传输提高了器件单粒子翻转的敏感性。电学特性表明,全三维器件数值仿真的方法能够有效评估因内建电势突变产生的瞬态脉冲电流。该方法满足器件仿真对精确度的要求。     

AlGaN/GaN HEMT中慢瞬态的数值解释

观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.     

Numerical Explanation of Slow Transients in an AlGaN/GaN HEMT

观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.     

三栅FET的总剂量辐射效应研究

通过对赝MOS进行不同剂量的辐射,得到不同辐射条件下赝MOS器件的I-V特性曲线,并通过中带电压法进行分析,得出在不同辐射下SOI材料的埋氧层中产生的陷阱电荷密度和界面态电荷密度参数。采用这些参数并结合Altal三维器件模拟软件模拟了硅鳍(FIN)宽度不同的三栅FET器件的总剂量辐射效应,分析陷阱电荷在埋氧层的积累和鳍宽对器件电学特性的影响。     

二氧化硅薄膜驻极体的电荷特性

对二氧化硅薄膜驻极体中几种主要电荷的基本特性－固定氧化物电荷的特性特性、氧化物陷阱电荷的特性及硅－二氧二硅界面陷阱电荷的特性进行了分析。     

全光增益钳制掺铒光纤放大器的瞬态特性研究

利用数值模拟方法对全光增益筘制EDFA的瞬态特性进行了系统的理论分析,着重研究了瞬态过程中系统参量（泵浦功率、环路损耗、上下载速度、上下载信道功率、钳制激光振荡波长等）对剩余信道驰豫振荡特性的影响;根据数值模拟结果,给出了全光增益箝制EDFA的优化设计思路。     

Analysis of surface state effect on gate lag phenomena in GaAsMESFET's

A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured “hole-trap-like” DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N⁺-gate spacing and lower surface state densities are shown to have less gate lag effect     

Hot electron induced degradation of undoped AlGaN/GaN HFETs

This work presents the effects of hot electron stress on the degradation of undoped Al_0.3GaN_0.7/GaN power HFET’s with SiN passivation. Typical degradation characteristics consist of a decrease in the drain current and maximum transconductance, an increase in the drain series resistance, gate leakage and a subthreshold current. Degradation mechanism has been investigated by means of gate lag measurements (pulsed I-V) and current-mode deep level transient spectroscopy (DLTS). Stressed devices suffered from aggravated drain current slump (DC to RF dispersion) which indicates possible changes in surface charge profiles occurred during hot electron stress test. The DLTS was used to identify the trap creation by hot electron stress. The DLTS spectra of stressed device revealed the evidence of trap creation due to hot electron stress.     

高功率条件下MOSFET栅电荷特性的测量方法

提出了一种高功率条件下MOSFET栅电荷特性的有效测量方法。在半桥电路的下管开启过程中,沟道出现高电流和高电压同时存在的情况,产生很高的瞬态功率。对于传统栅电荷测试方案,这不仅要求直流电源具备相当的功率输出,而且会在高功率区产生严重的自热效应,无法得到准确的栅电荷特性曲线。文章基于栅电荷测试的基本物理过程和关系,通过测量大电压-小电流与大电流-小电压下的栅电荷特性,获得了高功率条件下MOSFET的栅电荷特性。结果表明,该方法得到的栅电荷特性曲线及参数值与标准规格书的结果非常接近,具有很好的工业应用价值。     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

Numerical analysis of frequency dispersion of transconductance inGaAs MESFETs

A fully two-dimensional numerical model for the transconductance dispersion in GaAs MESFETs is presented. According to simulated results, the dominating surface traps belong to the hole trap type in order to obtain consistent results with reported measurements. The AC frequency-dependent modulation of negative surface charge can explain this anomalous phenomenon. The holes injecting from and emitting out of the gate metal electrode interact with the surface hole traps, and result in the change of the gate-to-source and the gate-to-drain resistances, which in turn cause the change in transconductance. The gate voltage and the gate length effects on the dispersion are also considered. Good agreement with reported results is obtained     

Investigation of current collapse and recovery time due to deep level defect traps in β-Ga2O3 HEMT

In this paper, drain current transient characteristics of β-Ga₂O₃ high electron mobility transistor (HEMT) are studied to access current collapse and recovery time due to dynamic population and de-population of deep level traps and interface traps. An approximately 10 min, and 1 h of recovery time to steady-state drain current value is measured under 1 ms of stress on the gate and drain electrodes due to iron (Fe)–doped β-Ga₂O₃ substrate and germanium (Ge)–doped β-Ga₂O₃ epitaxial layer respectively. On-state current lag is more severe due to widely reported defect trap E_C – 0.82 eV over E_C – 0.78 eV, −0.75 eV present in Iron (Fe)-doped β-Ga₂O₃ bulk crystals. A negligible amount of current degradation is observed in the latter case due to the trap level at E_C – 0.98 eV. It is found that occupancy of ionized trap density varied mostly under the gate and gate–source area. This investigation of reversible current collapse phenomenon and assessment of recovery time in β-Ga₂O₃ HEMT is carried out through 2D device simulations using appropriate velocity and charge transport models. This work can further help in the proper characterization of β-Ga₂O₃ devices to understand temporary and permanent device degradation.     

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.     

B-Spline Based, Large-Signal DC and Microwave-Model for SOI MOSFETs

We present a large/small-signal, non-quasi-static, charge conserving, SOI MOSFET modeling technique suitable for DC and high frequency circuit design. The device model is extracted from small signal microwave iso-thermal Y-parameter data and DC I–V characteristics. Low frequency dispersions associated with self-heating and floating body effects are verified to not limit the performance of this technique since it relies on both DC and transient I–V characteristics. The technique is applied to the modeling of a short-channel, partially depleted, SOI nMOSFET simulated on PISCES. The model generated is incorporated into a circuit simulator, which is used to perform large-signal transient and harmonic balance simulations. The transient I–V and gate charge extracted from the iso-thermal small-signal microwave Y-parameters, are in excellent agreement with the iso-thermal transient I–V and gate charge obtained from PISCES, respectively. The model topology is extended with a parasitic bipolar sub-circuit which automatically calculates the DC operating point for self-biasing circuits. Transient and non-linear power characterization results predicted with this model agree well with those obtained from PISCES for a wide range of input power drives. A complete electro-thermal model is proposed and verified to be able to predict temperature and transient I–V response.     

Effects of plasma charging damage on the noise performance ofthin-oxide MOSFET's

The effects of plasma charging damage on the noise properties of MOSFET's which is a necessary consideration for high-performance analog applications were studied using 1/f noise, Random Telegraph Signal (RTS) noise and charge pumping techniques. Plasma ashing significantly increases the drain flicker noise, more with larger antenna sizes, mainly in the low-frequency and low-gate-bias regime. The observed RTS reveals that an oxide trap with a few milliseconds time constant was induced by the plasma processing. This oxide trap is located in the energy space which corresponds to the low gate bias of device. This trap may be reproduced by Fowler Nordheim stress as suggested by noise and charge pumping measurements, supporting the notion that plasma ashing damage is a result of electrical stress, not radiation, for example     

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO₂ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO₂ dielectrics to thin stacked gate dielectrics are discussed