AutoCAD二次开发中特殊矩形绘制的研究

为了提高标牌行业绘制标牌的工作效率,操作流程的标准化,研究标牌参数化绘制方法及技术,结合Object ARX2008与C#进行了Auto CAD的二次开发,详细阐述了标牌参数化绘图系统的结构、设计流程以及应用设计结果进行参数化绘图的过程,使标牌企业绘制人员在绘制的过程中,只需输入必要参数就可以由计算机自动绘制的标牌特殊矩形,从而大大提高了工作效率并扩展了CAD二次开发的范围。     

基于ObjectARX的标牌曲线文字绘制的研究

为了提高标牌行业的绘制标牌的工作效率,操作流程的标准化,研究标牌参数化绘制方法及技术,结合（）NectARX2008与VisualStudio2008中的c。进行了AutoCAD的二次开发,详细阐述了标牌参数化绘图系统的结构、设计流程以及应用设计结果进行参数化绘图的过程,使标牌企业绘制人员在绘制的过程中,只需输入必要参数就可以由计算机自动生成所要绘制的曲线文字,从而大大提高了工作效率并扩展了CAD二次开发的范围。     

AuToCAD在室内家装制图中的应用

AuToCAD软件能够根据使用需求绘制出室内施工图纸,对于室内设计师来说极其重要。室内设计师应当熟练使用AuToCAD软件并掌握规范的制图方法。为帮助新人设计师掌握规范绘制一整套室内家装设计平面图纸的方法,文章以一套室内家装户型图设计为例,介绍AuToCAD软件制作施工图的步骤及流程,着重介绍平面图纸绘制中的注意事项及规范制图要求。希望能为刚刚步入室内家装设计行业的新人设计师提供一些参考经验,并规范制图方法。     

基于ObjectARX的标牌参数化绘制的研究

为了提高标牌行业中绘制标牌的工作效率,操作流程的标准化,研究标牌参数化绘制方法及技术,结合Object-ARX2008与Visual Studio2008中的C#进行了Auto CAD的二次开发。详细阐述了标牌参数化绘图系统的结构、设计流程以及应用设计结果进行参数化绘图的过程,使标牌企业绘制人员在绘制的过程中,只需输入必要参数就可以由计算机自动生成所要绘制的标牌。只要调整必要的参数就可以实现标牌的动态修改,从而大大提高了工作效率并扩展了CAD二次开发的范围。     

浅析管道断面速成软件的原理与应用

当前通信管道制图均以手工绘制为主,市面上大量第三方制图插件均不能满足管道断面的复杂变化,与现有建设标准不统一,适用性不高。文章从实践出发,结合同沟不同井的制图环境,深度定制管道断面制图插件。通过设置相应参数自动绘制出所需的管道断面图,快速标注运营商管道占孔排位,减少人工重复劳动的工作量,提高制图效率。     

机械制图中常用绘图技巧与问题分析

机械制图是目前机械设计领域最为重要的工作内容之一.文章通过对常见的机械设计方法和原则进行介绍,对机械制图领域常见的轴套类零件、盘盖类零件、叉架类零件、箱体类零件等制图标注方面的技巧进行阐述,并对零件设计尺寸标注常见问题与分析思路结合实例进行介绍,为相关制图人员提供参考.     

轴承端盖零件的参数化系统设计及NC加工仿真

轴承端盖零件在机械行业中使用非常广泛,但是其种类繁多,设计及绘图非常烦琐,效率低下。从参数化的设计技术出发,基于Pro/ENGINEER软件平台,应用Pro/Toolkit和VC++对其进行二次开发,建立了轴承端盖零件三维参数化造型系统。该系统能够通过修改相应尺寸参数生成不同的零件模型,再根据生成的零件模型利用Pro/Engineer设计出对应的模具,并采用Mastercam软件对已经设计好的模具进行数控加工仿真。     

基于组合单元库的零件CAPP技术研究

随着机械产品生产技术的发展,用计算机辅助工艺过程设计(Computer Aided Process Planning,CAPP)代替传统的工艺设计方法具有重要的意义,但各类零件的结构复杂性为CAPP系统的设计带来了困难。文中针对CAPP系统中零件信息的描述提出了组合单元库的解决方法,重点就基于组合单元库零件信息的CAPP进行了分析研究,从工艺数据库的建立、零件信息的输入及计算机辅助工艺决策3个方面进行了论述。并以回转类零件为例,在VFP6.0的环境下建立工艺数据库并进行了工艺决策系统的开发,利用菜单引导用户操作自动生成零件加工工艺过程的报表。通过对不同零件类别进行组合单元库的建立,可使CAPP系统中的零件输入系统简化,较好的完成了CAPP系统任务。     

基于S0lidWorks的真空灭弧室零件参数化系统的研究

以三维造型软件Solid Works2005为平台,采用参数化的设计思想,以Visual Basic 6.0为开发工具,建立了真空灭弧室零件参数化系统.系统给每一个零件创建了一个单独的设计界面,方便用户对真空灭弧室的每一个零件使用本系统进行参数的输入、确认,生成零件的三维模型,供用户后期的处理.通过使用本系统,必将极大地提高真空灭弧室设计过程中零件造型的速度,提高零部件设计的效率.     

磨削砂轮参数化设计的软件实现及加工仿真

成形磨削是现代加工生产过程中的一种先进的加工方法,而磨削砂轮的精度直接影响被加工零件的加工精度。本文依据砂轮母线的类型根据加工要求进行参数化设计,并基于参数化设计开发了成型砂轮参数化设计软件。根据实际需求该软件分为自动加工模块与手动加工模块,同时可自动生成可被常规数控系统所识别的NC代码,用于在数控软件中模拟刀具运动情况。     

稀布圆阵的降维优化方法

针对有阵列孔径,阵元数目和最小阵元间距3种约束下的稀布圆形阵列综合问题,该文提出了一种基于修正遗传算法的降维优化方法。为了充分利用阵元布阵的自由度,同时使稀布阵列满足多个设计约束,在阵元排布时将2维平面阵列优化设计降维成1维的稀布直线阵列,计算阵列性能时再还原为平面阵列。该方法改进了现有圆阵综合方法中轨迹圆半径和轨迹圆上阵元数分布优化的不足,实现了全部阵元的联合优化,降低了算法的复杂性,同时保证了阵列的旁瓣性能,仿真结果证明了该方法的有效性。     

Implementation of a 16 to 16 switching element for ATM exchanges

The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity     

Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem

The bridged T-coil (BTC) circuit is often employed to extend the bandwidth of a wideband amplifier beyond the transition frequency f_T of the driver device. Although the optimal design solution is well known, extreme algebraic complexity has caused its derivation to remain arcane. This brief presents an analysis of the BTC circuit using the extra element theorem which breaks the overall problem down into a series of simple network analyses and produces the final result as the product of the transfer function without the "extra element" and a multiplicative correction factor. The design is completed by using pole-zero cancellation to reduce the order of the transfer functions     

一种宽带恒定束宽DBF技术实现方法

针对常规DBF方法不适用于宽带信号的问题提出一种宽带恒定束宽DBF方法.根据空间重采样理论将均匀线阵视为空间离散采样,利用内插定理得到各阵元在不同频点上的加权系数矩阵.利用维纳滤波理论设计宽带波束合成器拟合加权系数矩阵,实现宽带内波束指向一致,宽度相等.给出了理论分析依据及仿真结果,仿真结果表明了该方法具有计算复杂度低、稳健性强的优点.     

空间遥感器反射镜组件结构设计方法

针对空间遥感器反射镜组件的结构复杂性和高性能需求,对空间遥感器反射镜组件的设计方法进行了研究。提出了一种经验设计、拓扑优化与尺寸参数优化相结合的设计方法,该方法可使设计结果快速收敛,获得最优化的设计结构。采用该方法完成了某空间遥感器反射镜组件的结构设计,通过有限元分析的手段得到了表征反射镜成像质量的RMS值,同时对整个反射镜组件进行了动力学分析计算,最后利用环境试验对有限元分析结果的正确性和设计的合理性进行了验证。结果表明:在重力载荷、温度载荷、镜面加工残差和装配误差的综合影响下,反射镜组件面形误差RMS值满足使用要求;整个结构有一个好的动态刚度和合理的模态分布,反射镜组件动态性能优良,满足使用要求。针对反射镜组件的设计,该设计方法是一种有效的、可靠的设计方法。     

一种高速大容量背板的设计与实现

背板是通信设备的要求.采用传统的板卡平行连接结构的背板,要继续增加带宽已经非常困难,从而成为制约系统容量的一个瓶颈.本文给出了一种采用前后交叉连接结构的高速大容量背板的具体设计实现,在保证信号完整性前提下大大降低了设计难度,其总带宽达到1Tb/s.     

基于LTCC的小型化中频带通滤波器设计

采用LTCC技术实现滤波器时,大电感值会引起加工复杂、寄生参数多等问题。文中通过部分电路等效法(PEEC)、三角形和星形联结等效变换法,将二阶直接耦合滤波器中的三角形连接电感等效为两个并联的耦合电感,减少了电感数量及感值。使得滤波器的设计复杂程度降低,标准化程度及一致性更高,封装更小。最终实现了一个中心频率70 MHz、相对带宽14.28%、插入损耗1.83 dB、回波损耗＜-15 dB的小型化中频滤波器。     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

A Processor-In-Memory Architecture for Multimedia Compression

This paper presents the design and development of a novel, low-complexity processor-in-memory (PIM) architecture for image and video compression. By integrating a novel-processing element with SRAM, bandwidth is improved and latency is greatly reduced. This paper also presents PIM design techniques for reduced power, area, and complexity for rapid deployment and reduced cost. A design methodology is presented and followed by an analysis of the processing element performance and capabilities. The proposed datapath solution delivers between 2 to 40 times higher performance compared to other presented solutions. The architecture executes a discrete cosine and wavelet transforms achieving up to 40% higher throughput per watt and occupying as little as 0.9% area compared to a commercial digital signal processing and other application-specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed processor-in-memory is implemented in 1.8-V 0.18-mum CMOS technology and operates with a 300-MHz clock     

Computer-aided device modeling and design procedure for current hogging logic (CHL)

Modeling of functional devices requires computer simulation of lateral and vertical device structure due to geometrical complexity. It not only must meet the requirements of network analysis programs, but also has to enable quantitative design. For the basic element of current hogging logic (CHL), the computer simulation of the two-dimensional situation has resulted in and given justification for a simple model approximating the injection performance and enabling quantitative design of even complex CHL circuits.