The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

A BiCMOS process utilizing selective epitaxy for analog/digitalapplications

A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an f_T of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

A deep-submicrometer microwave/digital CMOS/SOS technology

0.35-μm complementary metal-oxide-semiconductor (CMOS)/silicon-on-sapphire (SOS) n- and p-channel MOSFETs with a metal-over-polysilicon T-gate structure for monolithic microwave integrated circuit (MMIC) and digital applications are reported. The measured values for the current-gain cutoff frequency f_T were ⩾20 GHz for both n-channel and p-channel devices, and the values for the unilateral power-gain cutoff frequency f_max were 37 GHz for the p-channel and 53 GHz for the n-channel MOSFETs. The low effective resistance of the T-gate structure contributed to the very high f_max values. It is believed that these are the highest f_T and f_max values ever reported for MOS devices. The potential of SOS submicrometer MOSFETs for microwave circuit applications is demonstrated     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A 76-MHz BiCMOS programmable logic sequencer

A BiCMOS programmable logic sequencer with a maximum operating frequency of 76 MHz at a power dissipation of 370 mW has been developed. The device is organized as 16 inputs, 48 product terms, and eight registered outputs. The excellent speed power performance and TTL/CMOS compatibility were realized by an optimized circuit design coupled with an advanced BiCMOS process. The process features 13-GHz bipolar transistors, 1- mu m CMOS, TiW fuses, poly resistors, three-layer metal, and single-layer polycide. Bipolar devices are used in areas that utilize their strengths such as high current drivers, small-signal sensing, and precise current sources. CMOS is used in other areas to conserve layout size and power.<>     

Suppression of lateral autodoping from arsenic buried layer byselective epitaxy capping

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C_cs) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent     

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-MbDRAM's

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted