The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Monolithic integration of Si MOSFET's and GaAs MESFET's

Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 Å. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.     

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

GaAs/AlGaAs and InGaAs/AlGaAs MODFET inverter simulations

Although MODFET's have exhibited the fastest switching speed for any digital circuit technology, there is as yet no clear consensus on optimal inverter design rules. We therefore have developed a comprehensive MODFET device model that accurately accounts for such high gate bias effects as transconductance degradation and increased gate capacitance. The device model, which agrees with experimental devices fabricated in this laboratory, is used in the simulation of direct-coupled FET logic (DCFL) inverters with saturated resistor loads. Based on simulation results, the importance of large driver threshold voltage not only for small propagation delay times but for wide logic swings and noise margins is demonstrated. Furthermore, minimum delay times are found to occur at small supply voltages as seen experimentally. Both of these results are attributed to the reduction of detrimental high gate bias effects. The major effect of reducing the gate length on delay time is to decrease the load capacitance of the gate. Using 0.25-µm gates, delay times of 5 and 3.6 ps at 300 and 77 K, respectively, are predicted. Finally, the recently introduced In-GaAs/AlGaAs MODFET's are shown to have switching speeds superior to those of conventional GaAs/AlGaAs MODFET's.     

Properties of MODFET's grown on Si substrates at DC and microwave frequencies

We report the first microwave characterization of 1-µm gate GaAs/AlGaAs modulation-doped field-effect transistors (MODFET's) grown on Si substrates by MBE. Maximum transconductances of 170 mS/mm at room temperature were obtained in structures on Si, which compares to values of 200-250 mS/mm for this type of structure on GaAs. At 77 K, no collapse was observed in these structures, and transconductances of 270 mS/mm were obtained. From microwave S-parameter measurements at room temperature, current gain cutoff frequencies of 15 GHz were obtained from these GaAs/AlGaAs MOD FET's on Si, which compares with 12-15 GHz obtained on GaAs substrates. From high-frequency equivalent circuit modeling, very little difference was observed in any of the parameters between growth on Si and on GaAs. This is significant in that it demonstrates the suitability of GaAs on Si for device applications.     

Monolithic integration of GaAs/AlGaAs double-heterostructure LED's and Si MOSFET's

Fully monolithic integration of interconnected GaAs/Al-GaAs double-heterostructure LED's and Si MOSFET's is demonstrated for the first time. The Si MOSFET's, with a gate length of 5 µm and gate width of 1.6 mm, have almost the same characteristics as those of control devices fabricated on a separate Si wafer. The LED output collected by a microscope lens with a numerical aperture of 0.65 is about 6.5 µW at 100- mA dc current. LED modulation rates up to 27 Mbit/s have been achieved by applying a stream of voltage pulses to the MOSFET gate. The modulation rate is limited by the speed of the MOSFET.     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs     

Bias dependence of capacitances in modulation-doped FET's at 4 GHz

Scattering-parameter measurements were made on 1.0- µm gate normally-on and 1.6-µm gate normally-off modulation-doped field-effect transistors (MOD/FET's) as a function of bias at 4 GHz. A maximum oscillation frequency of 38 GHz, which is about 8 GHz larger than that for a comparable GaAs MESFET, due to larger transconductances for the MODFET's, was obtained. The input capacitance was found to vary more than expected with gate bias, while the feedback capacitance was nearly independent of bias in the saturation regime. Output capacitance increases as Vgsapproached the pinchoff voltage. These results should be of great importance in large-signal modeling of integrated circuits based on modulation-doped FET's.     

Quasi-Fermi level bending in MODFET's and its effect on FET transfer characteristics

Using Shockley's diffusion/drift model we calculate the quasi-Fermi level (imref) bending in the depleted AIGaAs barrier layer of GaAs/AIGaAs MODFET's. We show that the assumption of a constant imref from the heterointerface through the barrier layer is not justified when the gate is moderately forward biased. Once the barrier-layer conduction band edge at the gate interface fails below that at the heterointerface, the imref changes both in the vicinity of the heterointerface and at the gate metal. This has important consequences for the MODFET transfer characteristics and necessitates new considerations for the gate control mechanism As a result, sheet electron concentrations in the MODFET channel exceeding the equilibrium concentrations are obtained. Despite the gate being forward biased with voltages close to or larger than the Schottky-barrier height, the gate current is suppressed not only by the barrier at the heterointerface but also by a barrier of about the same height present at the gate metal-semiconductor interface. Experimental results on AIGaAs/GaAs MODFET's are in good quantitative agreement with the theoretical calculations.     

GaAs microwave MOSFET's

GaAs microwave metal-oxide-semiconductor field-effect transistors (MOSFET's) with plasma-grown native oxides as gate insulator have been fabricated using a low-temperature magnetically controlled plasma-oxidation technique. A small-signal enhancement device with the gate length of 2.0 µm has demonstrated useful unilateral power gains in the 2-8-GHz frequency range. A maximum frequency of oscillation in the enhancement device is 13 GHz. This is the highest in all enhancement-mode GaAs devices reported up to this time. A medium-power depletion device with the gate length of 1.8 µm has the maximum frequency of oscillation of 22 GHz. This value is 10 percent larger than that of the best analogous metal-semiconductor field-effect transistor (MESFET). The intrinsic current-gain cutoff frequency for the depletion MOSFET is 4.5 GHz which is 22 percent higher than that of the MESFET. The superiority of the depletion MOSFET in the small-signal microwave performance over the MESFET results from the smaller gate parasitic capacitance in the MOSFET as compared to the MESFET. The depletion MOSFET has produced 0.4-W output power at 6.5 GHz as a Class A amplifier. Quite a large frequency dispersion of transconductance is observed in the enhancement MOSFET at a frequency range between 10 and 100 kHz and attributed to interface states. The effect of the interface states does not severely restrict the microwave-frequency capabilities of the enhancement MOSFET as well as the depletion MOSFET since the interface states are unable to follow the input-signal variations at high frequencies.     

Gate capacitance—Voltage characteristic of MODFET's: Its effect on transconductance

Gate capacitance Cgin modulation-doped field-effect transistors (MODFET's) is one of the most important parameters for small- and large-signal applications as well as for understanding device operation at dc and high frequencies. We have modeled the gate capacitance-voltage characteristics of AlGaAs/GaAs MODFET's and obtained good agreement with experiments at 300 and 77 K. Rigorous numerical simulations relating the Fermi level at the GaAs/AlGaAs heterointerface to the two-dimensional electron gas (2DEG) concentrations were fitted with analytical functions to simplify the model. The fit is quite reasonable with an accuracy of 1 percent in a wide range of sheet carrier concentrations. By incorporating AlGaAs charge response to gate voltage near full turn-on, discrepancies between the experiments and earlier models (predicting a nearly constant capacitance-voltage characteristic) were minimized. The model also shows that theC_{g}(V)characteristic below threshold is governed by the doping level in the buffer layer, in the intermediate region by the 2DEG and near complete turn-on by the 2DEG and the AlGaAs layer. Considering the contribution of the AlGaAs layer, a detailed RC network was developed. The model also explains the rise in capacitance and fall in the transconductance for large forward gate voltages (low frequency) due basically to the contribution of AlGaAs to the gate capacitance but almost no contribution to the current conduction. In contrast, the transconductance and capacitance both increase in MESFET's.     

Short channel characteristics of Si MOSFET with extremely shallowsource and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system     

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD withpreheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g_m of n-MOSFET with 40-nm epitaxial Si for 0.10-μm gate length was 630 mS/mm at V _d-1.5 V, and the drain current was 0.77 mA/μm. This g_m value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices     

Ballistic and tunneling GaAs static induction transistors:nano-devices for THz electronics

GaAs static induction transistors (SIT) with 10-nm scale channel and with a 100-nm channel were fabricated with molecular layer epitaxy (MLE). Area-selective epitaxy of GaAs/AlGaAs/GaAs was used for the gate. Temperature dependence of current-voltage (I-V) characteristics of the 100-nm SIT indicates ballistic injection of electrons. In the 10-nm scale SIT, electrons are transported ballistically in the drain-side electric field. Direct tunneling is responsible for the transport through the potential barrier. It is indicated by the temperature dependence and by the electroluminescence spectrum. Electron transport in the 10-nm scale SIT is nearly scattering-free. The plausible estimation of the electron transit time is 2·10^-14 s; the worst case estimation based on saturated drift velocity gives 1·10^-13 s. It makes the ISITs suitable for THz applications. Multiple area-selective MLE GaAs regrowth was used as a tool for automatic definition of the channel length     

Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.     

Double pocket architecture using indium and boron for sub-100 nmMOSFETs

A double pocket architecture for sub-100 nm MOSFET's is proposed on the basis of indium pocket profiling at higher dose than the amorphization threshold. At high dose, the low-energy indium pockets realize the improvement of short channel effects and shallow extension formation of a highly doped drain, maintaining the low junction leakage level. A double pocket architecture using indium and boron is demonstrated in a 70 nm gate length MOSFET with high drive currents and good control of the short channel effects