Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger

In the present-day VLSI system, low power design plays a noteworthy role. As we know that, a circuit with higher power consumption can ruin the performance of the system because in the modern world most of the systems are portable. Subsequently, they are functioned by the batteries. Therefore, it is desirable to have a system which operates at lower supply voltages along with maintaining the performance of the system. This low power system can be attained by abating the leakages of the devices up-to an enormous magnitude. In the contemporary VLSI system, a major role is being contributed by the Schmitt trigger circuit. Schmitt trigger is fundamentally a comparator. It is implemented by using a positive feedback. The Schmitt trigger circuit is used in various devices such as buffer, sub-threshold SRAM, sensors and PWM circuit. It is also used in analog to digital converter. The most significant property of the Schmitt trigger is that they provide hysteresis in their voltage transfer curve. Consequently, they provide better noise immunity as compared to their counterparts. Therefore it becomes quite important to enhance the performance of the Schmitt trigger circuit. The power dissipation of the device can be minimized by minimizing the sub-threshold current. The Schmitt trigger circuit is very imperative in producing a clean pulse from the input signal comprising of noise. There are various applications of Schmitt trigger circuit such as in scheming the oscillator circuit, analog to digital converter, function generator, signal conditioning and numerous applications. Thus, it becomes noteworthy to boost its performance by plummeting the leakages and power consumption of the Schmitt trigger circuit. We have realized the Schmitt trigger circuit by the use of FinFET. Therefore, we have got some optimum output in the parameters such as hysteresis width, power consumption and total noise of the Schmitt trigger circuit, but the leakages have been augmented. Thereafter, we have implemented several techniques on the Schmitt trigger circuit to shrink the leakage current, leakage power and other parameters further. We have applied Self Controllable Voltage Level, Adaptive voltage level and MTCMOS technique on the Schmitt trigger circuit using FinFET to further augment the presentation. All the circuits have been simulated in the virtuoso tool of the cadence in 45 nm VLSI domain. We have applied 0.7 V of the supply voltage to perform the simulation and got some tremendous outcome.     

Low power Schmitt trigger circuit

Three new Schmitt trigger circuits are described. The first circuit is a truly low power, while the second and third circuits are derived from the first circuit and provide smaller hysteresis width. Measurement results for the new Schmitt trigger circuits are presented. All the designed circuits are simulated using HSPICE with level 28 model parameters for a 1.2 μm standard CMOS technology. An application to the design of low power, very low frequency integrator oscillators is described     

22 nm FDSOI器件的制备与背偏效应研究

提出了一种基于后栅极工艺的22 nm 全耗尽绝缘体上硅(FDSOI)器件的制备方法。基于电学测试结果,分析了器件的基本性能,研究了背栅偏压对器件性能的影响。结果表明,器件的开关电流比比较高、亚阈值摆幅较小,符合产业的一般标准。背栅偏压对长沟道和短沟道器件的阈值电压均有明显的影响。电路设计人员可以根据不同需求,选择工作在正向体偏置(FBB)模式或者反向体偏置(RBB)模式的器件。     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger circuit has been realised, using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

Low voltage CMOS Schmitt trigger circuits

Two new low voltage Schmitt trigger circuits are presented which use a dynamic body-bias technique. The first circuit is designed for operation at 1 V. The second circuit, derived from the first circuit, is designed for operation at 0.4 V. Experimental results for the new Schmitt trigger circuits are presented.     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits

This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.     

A simple wide-band CMOS based true rms-to-dc converter

A simple integrable circuit technique for the realization of a wide bandwidth current-mode CMOS true rms-to-dc converter is proposed. The realization scheme is based on the implicit computation method that makes use of the characteristic of a CMOS squaring circuit, where the transistors are biased in their saturation regions. The conversion circuit consumes very low power due to the bias current of the circuit provided by the root-mean-square current I _RMS. The performance of the proposed circuit is studied through PSPICE simulation and experimental results.     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.     

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC–DC buck converter

A single-inductor dual-output (SIDO) DC–DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6–5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

弛张振荡器在高精度体温计芯片中的应用

设计了一款基于弛张振荡器的温度测量电路,通过参考/感应振荡器电路,将热敏电阻的阻值变化转变成数字化的频率信号送系统处理。弛张振荡器使用了具有施密特触发器相同功能的RS触发器,降低了芯片对工艺的要求,便于在低电压和宽温度范围正常工作。该温度测量电路被成功地应用于一款便携式电子体温计芯片,芯片采用0.5μm 1.5 V DMSP CMOS工艺,面积为1 250μm×1 260μm,在1.1 V的低电压下测量精度高达0.05°C,工作电流为30μA,待机电流为0.2μA。