Short-channel pMOSTs in a high-resistivity silicon substrate. I.Analytical model

The behavior of short-channel pMOS transistors (2.5-25 μm) in a high-resistivity silicon substrate (3-10 kΩ-cm), resulting from a 3-μm CMOS process, especially optimized for the integration of totally depleted p-i-n type detectors and their readout electronics, is described both qualitatively and quantitatively. Their behavior is examined both in the off-region, where bulk punchthrough and space-charge limitations prevail, and in the on-region. Simulations and experimental data show that these transistors exhibit a second linear region, referred to as quasi-linear region, instead of the normal saturation region     

Surface-passivated high-resistivity silicon as a true microwave substrate

This paper addresses the properties of a surface-passivated (enhanced) high-resistivity silicon (HRS) substrate for use in monolithic microwave technology. The detrimental effects of conductive surface channels and their variations across the wafer related to the local oxide and silicon/silicon-dioxide interface quality are eliminated through the formation of a thin amorphous layer at the wafer surface. Without passivation, it is found that the surface channels greatly degrade the quality of passive components in HRS by masking the excellent properties of the bulk HRS substrate and by causing a spread in parameters and peak values across the wafer. Moreover, it is seen that the surface passivation leads to excellent agreement of the characteristics of fabricated components and circuits with those predicted by electromagnetic (EM) simulation based on the bulk HRS properties. This is experimentally verified for lumped (inductors and transformers) and distributed (coplanar waveguide, Marchand balun) passive microwave components, as well as for a traveling-wave amplifier, through which also the integration of transistors on HRS and the overall parameter control at circuit level are demonstrated. The results in this paper indicate the economically important possibility to transfer microwave circuit designs based on EM simulations directly to the HRS fabrication process, thus avoiding costly redesigns.     

Formation of radiation defects in high-resistivity silicon as a result of cyclic irradiation and annealing

Transformation of radiation-induced defects in p ⁺-n-n ⁺ structures fabricated from highresistivity n-type silicon subjected to cyclic irradiation and annealing is investigated. The kinetic behavior of the increase in the concentration of the C_i-O_i defects is analyzed as a function of the detector fabrication process. During the second irradiation cycle a transformation of the defects, which were formed as a result of annealing of the original radiation defects, is observed. The appearance of “hidden” sources of deep center formation is revealed. It is established that the presence of a higher oxygen concentration, which arises in the samples as a result of the extended silicon oxidation process, results in a more active complex-formation of carbon-containing defects in comparison with samples with reduced oxygen content. Fiz. Tekh. Poluprovodn. 31, 299–304 (February 1997)     

The spreading resistance of a homogeneous slab on a high-resistivity substrate: Mixed boundary value solutions

The range of applicability of the mixed boundary value method for calculating spreading resistance is extended to a homogeneous slab with a disc contact source and backed by a substrate of arbitrary, but finite resistivity. Solutions are presented in terms of the spreading resistance correction factors and the source current density distributions for a slab of varying thickness and with various high resistivity substrates. In particular, the results for a thin slab indicate that, as the substrate resistivity increases, more and more of the source current is concentrated near the edge of the disc electrode.A comparison is made of the source current density and potential corresponding to the mixed boundary value method with those given by the uniform flux and the variable flux (power-loss) method. It is found that, except for large slab thicknesses, the source potential distributions for a slab with a high resistivity substrate are not strongly influenced by the particular form of the source current density distribution assumed in either the uniform flux or the variable flux method. In consequence, both these two methods yield correction factors which agree quite closely with those derived from the mixed boundary value method.     

High microwave and noise performance of 0.17-/spl mu/m AlGaN-GaN HEMTs on high-resistivity silicon substrates

AlGaN-GaN high-electron mobility transistors (HEMTs) based on high-resistivity silicon substrate with a 0.17-/spl mu/m T-shape gate length are fabricated. The device exhibits a high drain current density of 550 mA/mm at V/sub GS/=1 V and V/sub DS/=10 V with an intrinsic transconductance (g/sub m/) of 215 mS/mm. A unity current gain cutoff frequency (f/sub t/) of 46 GHz and a maximum oscillation frequency (f/sub max/) of 92 GHz are measured at V/sub DS/=10 V and I/sub DS/=171 mA/mm. The radio-frequency microwave noise performance of the device is obtained at 10 GHz for different drain currents. At V/sub DS/=10 V and I/sub DS/=92 mA/mm, the device exhibits a minimum-noise figure (NF/sub min/) of 1.1 dB and an associated gain (G/sub ass/) of 12 dB. To our knowledge, these results are the best f/sub t/, f/sub max/ and microwave noise performance ever reported on GaN HEMT grown on Silicon substrate.     

1.55 μm InGaAsP/InP laser buried in a high-resistivity epitaxiallayer on a semi-insulating InP substrate

A buried heterostructure (BH) 1.55 μm laser embedded in a high resistivity epitaxial layer on a semi-insulating substrate is described. This device has a planar surface and both a p- and an n-type electrode on the same side, facilitating integration of electronic devices. Its threshold current is typically 9 mA. Its small signal 3 dB modulation bandwidth was 14 GHz due to the reduction of device resistance and capacitance. No degradation was observed in an aging test at 50°C even after more than 3000 h     

Single injection, double injection and negative resistance in gold-doped high-resistivity silicon

A simplified explanation is given for negative resistance in a semiconductor containing deep-lying donor and acceptor levels. A simple equation is derived for the breakover voltage and is verified by experimental studies of single and double-injection currents in gold-doped silicon.     

Noise in silicon double-base diodes

The power spectrum of the current fluctuations (noise) in the double-base diode has been measured experimentally and calculated theoretically. It has been found that there are two sources of noise in the double-base diode. First, there is the thermal noise of the real part of the ac admittance. The second source of noise is fluctuations in numbers of electrons and holes in the conduction band and valence band, respectively. Noise measurements are also presented for a diode with a long, high resistivity base region. These measurements are discussed qualitatively.     

Amorphous silicon phototransistor on a glass substrate

An amorphous silicon n⁺-i-p⁺-i-n⁺thin-film phototransistor was made on a glass substrate. The p⁺base is very thin (∼ 200 Å) compared with 2000 to 5000 Å of the collector i-layer. Therefore, the emitter current which is induced from the photogenerated flux in the collector i-layer is very high. In addition, hole lifetime (minority carrier in the emitter) and transit time are very short, the device possesses fast rise time and fall time of 30 µs, which is mainly governed by the junction capacitance-resistance charging effect and strays.     

Packaging compatible microtransformers on a silicon substrate

Surface micromachining techniques have been utilized to realize microtransformers on a silicon substrate for integration with a multi-chip package, allowing compact integration with chips, complementary metal-oxide-semiconductor (CMOS) circuits, sensors, and other components. Two different microtransformers comprised of two-layer vertically stacked spiral-type copper conductor lines and permalloy magnetic cores have been designed, fabricated, and characterized. Low temperature processes have been chosen for fabricating these microtransformers. The fabricated microtransformers have been tested and compared for finding out better geometries for integrated microtransformers. Electroplated thick permalloy cores and copper coils have been utilized for obtaining better performance characteristics in the intermediate frequency range. The fabricated microtransformers have a turn ratio of 1, coupling coefficient of 0.85, DC resistance of 3.3 /spl Omega/, and gain characteristics of -5 dB, respectively. They are suitable for integrated power converter applications, since these devices have also high current carrying capability (up to 2 A steady DC current).     

Effects of substrate resistances on LNA performance and a bondpadstructure for reducing the effects in a silicon bipolar technology

The effects of substrate resistances on the performance of 5.8-GHz low-noise amplifiers (LNAs) have been evaluated through a combination of experimental and simulation studies. The substrate resistive network for the LNA has been constructed by fabricating and measuring a test structure. The substrate resistances can be significantly affected by the die area and thickness, which raises a serious concern for on-wafer testing and optimization of circuits using the test results. The substrate resistances reduce the simulated gain by more than 10 dB and increase the noise figure by 2.7 dB. The simulation study has shown that the dominant substrate resistances are those associated with the bondpads. To reduce the effects of the substrate resistances, a ground-shielded bondpad structure, which consists of a Metal 2 pad and an n⁺ plug grounded shield separated by a composite oxide layer, has been developed. It reduces the resistance to ground to almost zero by conducting the signal away from the substrate to ground through the low-resistivity n⁺ plug layer. The pad structure in addition improves the interpad isolation by as much as 35 dB. However, to harness this isolation improvement, the inductance between the IC and PC board ground should be made small by using a low ground inductance package. Using this ground-shielded bondpad, the measured gain and noise figure of a 4.5-GHz tuned amplifier were improved by 10 and 2 dB, respectively, over the same circuit implemented using the conventional bondpad     

Noise spectra of a CW silicon TRAPATT oscillator

Noise measurements on a double-sided silicon TRAPATT oscillator have been made and show that the noise is comparable to that of the silicon IMPATT oscillator.     

Noise in epitaxial silicon bulk unipolar diodes

Silicon camel diodes with barrier heights in the range 0.46?0.94 eV were realised by means of low-pressure vapour phase epitaxy (LPVPE). These diodes show a conversion loss as low as 4.2 dB at 2 GHz and a noise figure of 4.8 dB.     

EM and substrate coupling in silicon RFICs

An investigation of coupling between inductors and resonators fabricated in silicon substrates is presented and the effects on RF systems and components are discussed. A novel experimental technique to measure inductor and resonator coupling is presented. The experiment is extremely sensitive, fast, accurate, and unique in that no matching, probe de-embedding, or calibration is necessary as the ratio of two on-chip signals is measured to yield the results.     

Nature of E c −0.37 eV centers and the formation of high-resistivity layers in n-type silicon

The DLTS and Van der Pauw methods are used to investigate the production of E _c −0.37 eV centers responsible for the formation of high-resistivity layers in n-type Si irradiated with electrons and annealed in the temperature range 80–320 °C. An analysis of the experimental data leads to a conclusion as to the composition of the E _c −0.37 eV centers ([V-O-C]) and to the conclusion that their formation is stimulated by a flux of interstitial atoms away from the interface into the interior of the semiconductor during annealing accompanied by the reactions: 1) I+C_s→C_i,C_i+[V-O]→[V-O-C] (dominant reaction); 2) I+V ₂→V,V+[C-O]→[V-O-C]. Fiz. Tekh. Poluprovodn. 31, 993–997 (August 1997)     

Noise performance of a Cartesian loop transmitter

The Cartesian loop transmitter is now a well-known linear transmitter architecture and is finding application in a number of mobile radio systems employing linear modulation technologies. In particular, systems utilizing π/4 DQPSK require a linear transmitter, and many emerging standards [e.g., trans-European trunked radio (TETRA)] provide applications for the Cartesian feedback linearization (CFL) technique. One problem with the CFL transmitter is that its output-noise performance is no longer dominated by that of the RF power module employed within it (as is the case in more conventional transmitter architectures). The use of significant degrees of attenuation, followed by a high level of gain, within the loop, means that the noise performance of the loop is significantly poorer than that of a conventional transmitter. There are a number of tradeoffs that are available to the designer of a CFL transmitter to aid in the optimization of the output-noise performance. This paper presents a derivation of the noise performance of a Cartesian loop transmitter and highlights the design methods that may be employed in order to optimize its noise performance. It also provides a comparison of the theoretically derived behavior with that of a practical transmitter operating in the TETRA (380-400 MHz) band     

Hole-traps in silicon dioxides. Part II. Generation mechanism

After studying the properties of hole traps in Part I, attention is turned to the physical processes responsible for generating hole traps in Part II of this work. The applicability of four models to hole-trap creation will be examined. These are the trapped hole-electron recombination model, the electrical field energy model, the hole injection model, and the hydrogen model. To testify these models, stresses have to be carried out not only under substrate hole injection (SHI), but also under Fowler-Nordheim injection (FNI). By combining FNI with SHI, we will be able to control hole fluency independent of the electron-induced hydrogen release. This allows us to determine how important hydrogen is for hole-trap generation. Although it was reported that hydrogen could play a major role in positive charge generation for devices with an Al gate or without a gate, we will show that hydrogen does not dominate hole-trap generation, when poly-si gated devices are stressed under our test conditions. Unambiguous results will also be given to show that key predictions of the recombination model and the electrical field energy model are not observed here. In this paper, the most important process for hole-trap generation is found to be the direct interaction of injected holes with the oxide.     

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity silicon substrates (HR-Si). Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps added to the mobility and carrier lifetime degradation, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation-induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide (t_ox = 50 nm), while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.     

DC and RF performance of GaAs MESFET fabricated on silicon substrate using epitaxial lift-off technique

GaAs MESFETs have been fabricated on a silicon substrate using a molecular beam epitaxy grown film detached from its growth substrate and attached on a silicon substrate covered with a dielectric. The device processing is done on the silicon substrate. The MESFETs exhibit I/sub DSS/=130 mA/mm, g/sub m/=135 mS/mm and for 1.3 mu m gate length unity current gain cut-off frequency f/sub T/ of 12 GHz. Excellent device isolation with subpicoampere leakage currents is obtained.<>     

Efficient BEM-based substrate network extraction in silicon SoCs

This paper is focused on the efficient extraction of the substrate network in complex system-on-chip designs. A boundary element method (BEM)-based approach, which employs spatial-frequency domain Green's function analysis, is considered and very high efficiency is achieved by a novel formulation of the boundary conditions which describe both resistive and capacitive couplings. The efficiency of the proposed technique is further increased taking advantage of the inherent information compression provided by the discrete cosine transform (DCT). The effectiveness of the proposed method is assessed by comparison with a commercial substrate extraction tool and its computational advantage is illustrated on the basis of computer simulation results.