用于Ka波段锁相环的宽带注入锁定分频器

基于0.13 μm CMOS工艺,提出了一种用于Ka波段锁相环频率综合器的宽带注入锁定分频器。分析了传统注入锁定分频器的结构、自谐振频率和锁定范围。采用2位可变电容阵列和差分信号互补谐振腔直接注入方法,实现了宽带的注入锁定分频。仿真结果表明,当注入信号幅度V_p为0.6 V时,该注入锁定分频器在24.1~35.6 GHz频率范围内的锁定范围为38.5%。与VCO联合仿真,结果表明,该分频器能准确实现二分频,适用于Ka波段锁相环。     

一种宽锁定范围的毫米波注入锁定分频器

基于GF 65 nm CMOS工艺,实现了一种宽锁定范围的毫米波注入锁定(IL)分频器。采用电流复用前置放大器和双端混频,有效扩大了分频器的锁定范围,并且不产生额外的功耗。电路仿真结果表明,当调节电压在0~1.2 V变化时,输入频率的锁定范围为81~110 GHz。工作电压为0.8 V时,电路的功耗为5.74 mW。该分频器适用于75~110 GHz的W-band系统。     

一种低功耗宽锁定范围注入锁定式分频器

设计了一种低功耗宽锁定范围的注入锁定式2倍分频器。该分频器基于环形振荡器结构,能够产生正交混频器所需的正交本征信号。分频器的环形振荡器采用两级结构,而不是多级结构,降低了功耗。采用TSMC 0.18μm CMOS工艺进行电路和版图设计。寄生参数提取后的仿真结果表明,该分频器频率锁定范围为3~12GHz,在1.8V电源电压下的最大功耗仅为1.8mW,具有低功耗、宽锁定范围的特点。     

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60 GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40 nm 1P6M RF CMOS工艺,芯片核心面积为0.016 mm²。仿真结果表明,在0.8 V电源电压下,电路功耗为5.5 mW,工作频率范围为55.2~61.2 GHz,注入锁定范围为6.0 GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。     

Ka波段AlGaN/GaN HEMT的研制

为了提高AlGaN/GaN HEMT的频率,采用了缩小源漏间距、优化栅结构和外围结构等措施设计了器件结构,并基于国内的GaN外延片和工艺完成了器件制备.测试表明所研制的AlGaN/GaN HEMT可以满足Ka波段应用.其中2×75μm栅宽AlGaN/GaN HEMT在30V漏压下的截止频率为32GHz,最大振荡频率为1...     

适用于OFDM UWB 系统的低功耗，大锁定范围注入锁定分频器

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

一种毫米波宽锁定范围的注入锁定倍频器设计

为提高毫米波段倍频器在低功耗下的工作带宽,采用IHP130 nm SiGe BiCMOS 工艺,设计了一种采用双端注入技术的毫米波宽锁定范围注入(DEI)锁定倍频器。该注入锁定倍频器主要由谐波发生器和带有尾电流源的振荡器构成,由巴伦产生差分信号双端注入振荡器的形式提高三次谐波注入强度,使其在E、W 等波段输出宽锁定范围和良好相位噪声性能的三倍频信号。仿真结果表明,注入锁定倍频器在工作电压为1.2 V,输入信号功率为0 dBm时,其锁定范围在57~105 GHz 内。在相同工作电压和输入信号功率下,输入频率为32 GHz 时,一次、二次和四次谐波抑制大于20 dBc,功耗为9.1 mW。     

基于注入锁定的RF低功耗正交本振信号产生电路

实现了一个基于注入锁定技术的射频低功耗正交本振信号产生电路.该电路由工作于两倍频频段的压控振荡器和两个注入锁定二分频器及缓冲器构成,可以为无线收发机提供正交本振信号.通过采用数字调谐技术,压控振荡器达到了很宽的调谐范围,而通过在注入锁定二分频器中加入与压控振荡器相同的变容管和电容阵列,保证了注入锁定二分频器在整个频带范围内都能保持锁定.该正交本振产生电路采用UMC 0.18 μm CMOS工艺实现.测试结果表明,在1.9～2.3 GHz频率范围内,该电路能够提供正交本振信号.该电路采用1.8 V电源供电,消耗的电流为2.2 mA(不包含缓冲器的电流),占用芯片面积为1.56 mm2.     

基于灯丝螺旋结构的S波段磁控管注入锁定技术

传统的磁控管注入锁定系统利用波导环行器隔离注入信号源和磁控管来实现高精度外部信号的注入,完成磁控管输出的控制。波导环行器及其配套的水负载和波导同轴转换器极大地提高了系统的成本和尺寸。针对上述问题,基于磁控管灯丝结构提出了一种新型注入锁定方式,通过对磁控管滤波盒的改造成功实现了无波导环行器下的注入锁定。该方法有效实现了注入锁定系统的小型化,为磁控管注入锁定的实现提供了新思路。     

基于AlN/GaN异质结的Ka波段GaN低噪声放大器研制

报道了基于AlN/GaN异质结的Ka波段低噪声放大器的研制结果.在SiC衬底上生长AlN/GaN异质结材料结构,采用电子束直写工艺制备了栅长70 nm的"T"型栅结构.器件最大电流密度为1.50 A/mm,最大跨导为650 mS/mm,通过S参数测试外推特征频率和最大频率分别为105 GHz和235 GHz.基于70 ...     

A wide-locking range 6-phase divide-by-3 injection-locked frequency divider

A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 μm CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of ?5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38–2.31 GHz.     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

LC-tank divide-by-4 injection-locked frequency divider using the second-order harmonic feedback

A low voltage, wide locking range and operation range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and the ILFD was fabricated in the TSMC 90 nm RF-CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and a three-transistor composite that acts as a linear and nonlinear mixer. At a drain-source bias of 0.6 V and at an incident power of 0 dBm, the operation range of the divide-by-4 ILFD is 5.3 GHz, from the incident frequency 21.1 GHz to 26.4 GHz, and the percentage of operation range is 22.31%. The locking range of the divide-by-4 ILFD is 1.4 GHz, from the incident frequency 21.1 GHz to 22.5 GHz, and the percentage of locking range is 6.42%. The core power consumption is 2.58 mW. The die area is 0.86 × 0.75 mm².     

应用于K波段的宽锁定范围低功耗注入锁定三倍频器

This paper presents a wide locking range and low DC power injection-locked frequency tripler for Kband frequency synthesizers application. The proposed ILFT employs a variable current source to decouple the injection signal path and the bias current so that the third harmonic of the injection signal can be maximized to enlarge the locking range. Meanwhile, a 2-bit digital control capacity array is used to further increase the output frequency locking range. It is implemented in a 130-nm CMOS process and occupies a chip area of 0.7 0.8 mm2 without pads. The measured results show that the proposed ILFT can achieve a whole locking range from 18 to21 GHz under the input signal of 4 d Bm and the core circuit dissipates only 4 m W of DC power from a 0.8 V supply voltage. The measured phase noise degradation from that of the injection signal is only 10 d B at 1 MHz offset.     

A low-voltage,low power divide-by-4 LC-tank injection-locked frequency divider

A low-voltage wide locking range injection-locked frequency divider (ILFD) using a standard 0.18?µm complementary metal-oxide-semiconductor process is presented. The ILFD is based on a differential LC VCO with one injection metal oxide semiconductor field effect transistor (MOSFET) for coupling external signals to the resonator. The low-voltage operation and wide locking range is obtained by boosting the gate voltage swing of the ILFD. Measurements show that at the supply voltage of 0.67?V, the divider's free-running frequency is tunable from 3.91 to 4.22?GHz, and the core power consumption is 1.87?mW. At the incident power of 0?dBm the divide-by-4 operation range is about 2?GHz (12.3%), from the incident frequency 15.3–17.3?GHz. The divide-by-2 locking range is about 5.1?GHz (77%), from the incident frequency 4.1–9.2?GHz.     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

7-27GHz 动态源极耦合逻辑二分频器

本文介绍了一款高速宽带二分频器的设计与分析。设计采用动态源极耦合逻辑结构,由两级动态负载主从D触发器构成,工作频率高,功耗低。这款分频器工作范围为7~27GHz,在1.2V工作电压下最低功耗仅为1.22mW。整个频带内输入灵敏度仅为25.4dBm。设计采用90nm CMOS工艺,使用了两个片上螺旋电感,芯片面积为685um*430um。     

基于Rb原子频标电注入锁定的高频稳低相噪光电振荡器

为了进一步改善光电振荡器(OEO)输出信号频 率的长期稳定度和相位噪声,提出了一种基于 Rb原子频标电注入锁定的单环OEO。将Rb原子钟产生的高频稳正弦信号注入到单环OEO,通过 注入信号与自由振荡信号的频率牵引,OEO获得单一振荡模式。实验发现,随着注入功 率的 增大,锁定带宽变大,锁定信号的相位噪声变差;随着注入功率的下降,锁定带宽变小,锁 定信号的相位噪声得 到改善,趋近于注入源信号的相位噪声。当光纤长取10km时,获得 了中心频率10GHz、边模抑制比大 于60dB、相位噪声的指标为－76dBc/Hz@100Hz和－108dBc/Hz@10kHz的输出信号,其输 出信号的长期稳定度和准确度得到改善。实验结果与理论分析一致。     

10～37GHzCMoS四分频器的设计

给出基于0．13μmCMOS工艺、采用单时钟动态负载锁存器设计的四分频器。该四分频器由两级二分频器级联而成。级间采用缓冲电路实现隔离和电平匹配。后仿真结果表明其最高工作频率达37GHz,分频范围为27GHz。当电源电压为1．2V、工作频率为37GHz时,其功耗小于30mW,芯片面积为0．33-0．28mm2。