Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in I_OFF of ～ 9 × 10^-16A/μm, I_ON of ～20 μA/μm, I_ON/I_OFF of ～2 × 10¹⁰, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO₂/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and V_DD of 0.2 V.     

Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。     

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

In this paper a two dimensional analytical model of channel potential and electric field for an asymmetric and symmetric double gate three-terminal (3T) and four-terminal (4T) silicon n-tunnel field effect transistor (Si-nTFET) device in sub-threshold region, without surface accumulation or inversion, is presented. Since the modeling has been done in subthreshlod regime operation, no Quantum Mechanical (QM) study has been taken. A very good agreement of analytically modeled results with the TCAD simulated results for the three-terminal (3T) and four-terminal (4T) Si-nTFET device was found. The model presented is based on the physics of the device. The modeling is for a 3T/4T asymmetric Tunnel FET and with appropriate changes in the device parameters we can also model for symmetric devices as well. The modeling scheme is thus quite robust.     

基于FDSOI的TFET和MOSFET总剂量效应仿真

对基于全耗尽绝缘体上硅(FDSOI)的隧穿场效应晶体管(TFET)器件和金属氧化物半导体场效应晶体管(MOSFET)器件进行了总剂量(TID)效应仿真,基于两种器件不同的工作原理,研究了总剂量效应对两种器件造成的电学影响,分析了辐照前后TFET和MOSFET的能带结构、载流子密度等关键因素的变化。仿真结果表明:两种器件在受到较大辐射剂量时(1 Mrad (Si)),TFET受辐射引起的固定电荷影响较小,仍能保持较好的开关特性、稳定的阈值电压;而MOSFET则受固定电荷的影响较大,出现了背部导电沟道,其关态电流增加了几个数量级,开关特性发生了严重退化,阈值电压也严重地向负电压偏移。此外,TFET的开态电流会随着辐照剂量的增加而减小,这与MOSFET的表现恰好相反。因此TFET比MOSFET有更好的抗总剂量效应能力。     

Comparison of Mg and Zn gate implants for GaAs n-channel junction field effect transistors

Zinc and magnesium implants into GaAs were profiled with secondary ion mass spectroscopy and etching capacitance-voltage to measure the as-implanted and annealed profiles for the eventual formation of shallow p⁺/n junction gates for junction field effect transistors (JFETs). The larger mass of the zinc ions results in shorter projected range with significantly less tailing than magnesium implants. High dose, shallow zinc implants annealed under tungsten gate metal showed good activation with negligible diffusion. The improved profile of the zinc implant, as compared to a similar magnesium implant, allowed a tighter JFET design with increased performance. Zn gated n-channel enhancement mode GaAs JFETs with 0.9 μm gate lengths showed transconductances up to 200 mS/ mm with a f_t of 18 GHZ and a f_max of 37 GHz. The performance of these self-aligned fully implanted JFETs compare favorably with comparably sized implanted MESFETs.     

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (I_OFF), its practical application is questionable due to low ON current (I_ON) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in I_ON. The enhancement in I_ON is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An I_ON of and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the I_OFF in fA range.     

Prospects and challenges of silicon/germanium on-chip optoelectronics

On-chip optoelectronics allows the integration of optoelectronic functions with microelectronics. Recent advances in silicon substrate fabrication (silicon-on-insulator (SOI)) and in heterostructure engineering (SiGe/Si) push this field to compact (chipsize) waveguide systems with high-speed response (50-GHz subsystems realized, potential with above 100 GHz). In this paper, the application and requirements, the future solutions, the components and the physical effects are discussed.A very high refractive index contrast of the waveguide Si-core/SiO2-cladding is responsible for the submicron line widths and strong bendings realized in chipsize waveguide lines and passive devices. The SiGe/Si heterostructure shifts the accessible wavelength into infrared up to telecommunication wavelengths 1.30-1.55 μm. Germanium, although also an indirect semiconductor as silicon, offers direct optical transitions which are only 140 meV above the dominant indirect one. This is the basic property for realizing high-speed devices for future above 10 GHz on-chip clocks and, eventually, a laser source monolithi-cally integrated on the Si substrate.     

锗硅表面结构和动态过程的STM研究

本文综述了我们利用扫描隧道显微镜和低能电子衍射对锗硅表面结构和动态过程进行了系统化和比较性的研究。研究结果除了具有重要的基础意义外，对半导体异上延生长衬底选择以及量子线和量子点自组织生长模板的选择都有指导意义。     

Design,modelling, and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

基于硅(111)晶面腐蚀的可控在线细化工艺及其对硅纳米线电学性能的改善

Nanoscale refinement on a (100) oriented silicon-on-insulator (SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide (TMAH, 25 wt%) anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the (111) crystal plane. Specifically for a silicon nanowire (SiNW) with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral (2.3 nm/min) and vertical (1.7 nm/min) dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor (FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the (111) plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.     

In situ nanoscale refinement by highly controllable etching of the(111) silicon crystal plane and its influence on the enhanced electrical property of a silicon nanowire

Nanoscale refinement on a(100) oriented silicon-on-insulator(SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide(TMAH,25 wt%) anisotropic silicon etchant,with temperature kept at 50℃to achieve precise etching of the(111) crystal plane.Specifically for a silicon nanowire(SiNW) with oxide sidewall protection,the in situ TMAH process enabled effective size reduction in both lateral(2.3 nm/min) and vertical (1.7 nm/min) dimensions.A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly,yielding enhanced field effect transistor(FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart,which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality ofthe(111) plane,as well as the bulk depletion property should be the causes of this electrical enhancement,which implies the great potential of the as-made cost-effective SiNW FET device in many fields.     

A computationally efficient model of single electron transistor for analog IC simulation

A compact analytical single electron transistor (SET) model is proposed. This model is based on the “orthodox theory” of single electron tunneling, valid for unlimited range of drain to source voltage, valid for single or multi-gate, symmetric or asymmetric devices and takes the background charge effect into account. This model is computationally efficient in comparison with existing models. SET characteristics produced by the proposed model have been verified against Monte Carlo simulator SIMON and show good agreement. This model has been implemented in HSPICE simulator through its Verilog-A interface to enable simulation with conventional MOS devices and single electron inverter has been simulated and verified with SIMON results. At high operating temperature, the thermionic current is taken into account.     

硫酸根离子敏感半导体器件的研究

本文报导一种基于四苯硼钠的离子敏感半导体器件。该器件的线性响应范围为 1 0×10 - 1- 1 0× 10 - 3mol/L ,斜率为 32ml/pc (13℃ ) ,检测下限为 6 0× 10 - 4mol/L。适宜的PH范围为 4 - 4 6。     

优化Hammerstein模型的电磁脉冲效应建模仿真

针对采用Hammerstein模型描述电磁脉冲效应时模型参数确定困难的问题,提出一种基于优化Hammerstein模型的非线性电磁脉冲效应建模仿真方法。该方法利用高阶累积量求解模型线性延迟阶数,采用赤池信息准则（Akaike Information Criterion,AIC）优化模型非线性阶次,两者共同确定出一个参数最少、精度较高的最优模型,并以瞬态抑制器的电磁脉冲效应建模为例验证了该方法。     

TFSOI RESURF功率器件表面电场分布和优化设计的新解析模型

提出了 TFSOI RESURF功率器件的表面电场分布和优化设计的新解析模型 .根据二维泊松方程的求解 ,得到了表面电场和电势分布的相关解析表达式 .在此基础上 ,推出了为获得最大击穿电压的优化条件。讨论了击穿电压和漂移区长度及临界掺杂浓度和场氧化层、埋氧化层的关系 .解析结果与半导体器件数值分析工具 DESSISE-ISE得到的数值分析基本一致 ,证明了新解析模型的适用性 .     

Observation of the quantum confined stark effect in ZnSe/ZnCdSe single quantum well systems

We report the observation of the quantum-confined Stark effect (QCSE) in ZnSe/ ZnCdSe single quantum wells grown by molecular beam epitaxy, using photoluminescence. In our experiments the electric field was applied via a reverse-biased Schottky barrier contact. To our knowledge, this is the first observation of the QCSE in any wide gap II-VI semiconductor heterostructure. Significant red shifts, typically 10–15 meV, are detected before quenching. An associated reduction in the transition intensity, consistent with the QCSE. is clearly observed. The dependence of these results will be discussed as a function of quantum well depth and thickness. Complete quenching of the luminescence is observed with applied voltages as low as 5 V. In addition, at lowest voltages, we also detect small blue shifts (up to 4 meV), which we attribute to the interaction between the externally applied electric field and the built-in field of the structure.