NiIn（Ge）／n－GaAs欧姆接触的研究

本文报道了一种用电子束蒸发制备铟基金属与ｎ型ＧａＡｓ单晶欧姆接触ＮｉＩｎ（Ｇｅ）／ｎ－ＧａＡｓ材料．其接触电阻率ρｃ对随后的热退火温度存在着典型的Ｕ型依赖关系．透射电子显微镜（ＴＥＭ）及俄歇电子能谱（ＡＥＳ）的分析结果指出ρｃ值的大小很大程度取决于ＧａＡｓ衬底与金属接触材料间ＩｎＧａＡｓ相的形成及其覆盖度．文中还对金属接触材料与砷化镓相互作用的动力学进行了讨论．     

Al／n—GaAs肖特基接触正向脉冲退化对GaAsIC的影响

本文描述了Ａｌ／ｎ－ＧａＡｓ肖特基接触的正向脉冲退化效应，探讨了当肖特基二极管承受正向电流冲击时，势垒高度ΦＢ升高，直接影响Ａｌ栅ＭＥＳＦＥＴｓ的特性，导致Ａｌ／ｎ－ＧａＡｓ ＩＣ失效的机理。     

微波功率GaAs MESFET的可靠性

本文介绍了功率ＧａＡｓ ＭＥＳＦＥＴ的必要失效模式和失效机理，主要失效模式有突然烧毁致命失效，缓慢退化失效，击穿低漏电大失效，内外引线和热集中失效，器件性能的不稳定和可逆漂移，主要失效机理有结构设计不合理，材料和工艺缺陷，栅结，欧姆接触和材料退化。静电损伤等，提出了改进功率ＧａＡｓ ＭＥＳＦＥＴＳ可靠性的主要措施：全面质量管理，运用可靠性增长管理技术，合理的设计方案，先进的设备和工艺，优质的材料和     

Au／AuGeNi／n－GaAs欧姆接触失效机理的研究

对Ａｕ／ＡｕＧｅＮｉ／ｎ－ＧａＡｓ欧姆接触进行了三种不同的应力试验：（１）高温存储（ＨＴＳ），（２）常温大电流（ＨＣ），（３）高温适当电流。试验结果表明，三种试验均造成了试验后期欧姆接触电阻增大，最后导致欧姆接触失效。ＡＥＳ分析表明，试验后的样品发生了Ｎｉ、Ａｎ和ＧａＡｓ的互扩散。     

GaAs MESFET直流特性退化的失效分析

ＧａＡｓ ＭＥＳＦＥＴ直流特性退化的主要原因是源极漏极欧姆接触退化和栅极肖特基势垒接触退化，笔者用结构敏感参数电测法和Ｃ－Ｖ法进行失效定位和失效分析，为上述失效原因提供了证据。     

Au／AuGeNi／n—GaAs欧姆接触失效机理的研究

本文对Ａｕ／ＡｕＧｅＮｉ／ｎ－ＧａＡｓ欧姆接触进行了三种不同的应力试验：（１）高温存储（ＨＴＳ），（２）常温大电流（ＨＣ），（３）高温适当电流。试验结果表明，三种试验均造成了实验后期欧姆接触电阻增大，最后导致欧姆接触失效。ＡＥＳ分析表明，试验后的样品发生了Ｎｉ，Ａｕ和ＧａＡｓ的互扩散。     

Pd／In／Pd等组分材料对n型GaAs欧姆接触的比较研究

Ｐｄ／Ｉｎ／Ｐｄ等组分材料对ｎ型ＧａＡｓ欧姆接触的比较研究《ＳｏｌｉｄＳｔａｔｅＥｌｅｃｔｒｏｎｉｃｓ》１９９５年第一期报导了Ｈ．Ｇ．Ｆｕ等对ｎ型ＧａＡｓ欧姆接触各种组分材料的比较研究，这些组分是Ｐｄ／Ｉｎ／Ｐｄ，Ｐｄ－Ｉｎ／Ｐｄ和Ｐｄ－Ｉｎ。其沉积...     

Au／AuGeNi／n－GaAs欧姆接触失效机理的研究

本文对Ａｕ／ＡｕＧｅＮｉ／ｎ－ＧａＡｓ欧姆接触进行了三种不同的应力试验：（１）高温存储（ＨＴＳ），（２）常温大电流（ＨＣ），（３）高温适当电流。试验结果表明，三种试验均造成了实验后期欧姆接触电阻增大，最后导致欧姆接触失效。ＡＥＳ分析表明，试验后的样品发生了Ｎｉ，Ａｕ和ＧａＡｓ的互扩散。     

Au／AuGeNi／n—GaAs欧姆接触失效机理的研究

对Ａｕ／ＡｕＧｅＮｉ／ｎ－ＧａＡｓ欧姆接触进行了三种不同的应力试验：（１）高温存储（ＨＴＳ），（２）常温大电流（ＨＣ）。（３）高温适当电流。试验结果表明，三种试验均造成了试验后期欧姆接触电阻增大，最后导致欧姆接触失效，ＡＥＳ分析表明，试验后的样品发生了Ｎｉ，Ａｕ和ＧａＡｓ的互扩散。     

P埋层技术研究

介绍了在Ｓｉ￣＋注入的ｎ－ＧａＡｓ沟道层下面用Ｂｅ￣＋或Ｍｇ￣＋注入以形成ｐ埋层。采用此方法做出了阈值电压０～０．２Ｖ，跨导大于１００ｍＳ／ｍｍ的Ｅ型ＧａＡｓＭＥＳＦＥＴ，也做出了夹断电压－０．４～－０．６Ｖ、跨导大于１００ｍＳ／ｍｍ的低阈值Ｄ型ＧａＡｓＭＥＳＦＥＴ。     

金-锗系统欧姆接触制备研究

对于 Ga As MESFET和以 Ga As或 In P为衬底的 PHEMT的欧姆接触制备 ,虽均采用 Au-Ge- Ni系统 ,但其合金条件却因材料特性各异而不同。     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

Monolithic optoelectronic circuit design and fabrication byepitaxial growth on commercial VLSI GaAs MESFET's

A technique for realizing large-scale monolithic OEIC's, which involves epitaxially growing GaAs-based heterostructures on fully metallized commercial VLSI GaAs MESFET integrated circuits, has recently been reported. In the initial work the circuits and LED's occupied distinct halves of a chip, the dielectric growth window was wet-etched after circuit fabrication, and the LED's required both n and p ohmic contacts to be formed after epitaxial growth. In this letter we report the use of standard foundry process etches to open dielectric growth windows intermixed with circuitry and the growth of n-side-down LED's on a source/drain ion-implanted n⁺ region serving as the n ohmic contact. A winner-take-all neural circuit is demonstrated using these advances, which are important steps toward realizing higher levels of circuit integration     

Si衬底上MBE GaAs MESFET与IC制备

叙述在MBE(分子束外延)GaAs/Si材料上制作GaAs MESFET与Ic的研究。考虑到GaAsIC与Si IC单片集成的需要,采用了Ti/TiW/Au肖特基金属化和Ni/AuGe/Ni/Au欧姆接触金属化,层间介质采用等离子增强淀积氮化硅和聚酰亚胺复合材料。在该工艺基础上,制备了性能良好的GaAs/Si MESFET与IC。     

A self-aligned ohmic metallization GaAs-Gate FET with integrated coupling diode

A novel processing scheme has been demonstrated for the fabrication of GaAs/AlGaAs semiconductor-insulator-semiconductor FET's (SISFET's). It was shown that a self-aligned ohmic (SAO) metal deposition could be used, without any additional ion implantation, to contact the two-dimensional electron gas (2DEG) of the SISFET. The process incorporates a coupling diode epitaxially grown atop the semiconductor gate (CDFL scheme [1]). Also, a depletion-mode MESFET was fabricated within the GaAs-gate layer in order to demonstrate the feasibility of a SISFET/MESFET inverter.     

A molybdenium source,gate and drain metallization system for GaAs MESFET layers grown by molecular beam epitaxy

Molecular beam epitaxy has been used in a continuous growth procedure to form GeGaAs epitaxial structures that were suitable for MESFET fabrication. Near surface doping profiles were engineered such that low resistance ohmic contacts to the GaAs layer were obtained by subsequently depositing a metal overlayer on the Ge surface. Evaporated Au overlayers yielded specific contact resistances of the order of 10^?6ω cm² without heat treatment. Because the conventional alloying procedure now appeared superfluous, metallurgically non-reactive systems were investigated with a view to constructing GaAs MESFETs with entirely refractory metallizations. Sputtered molybdenum has been evaluated for both the formation of ohmic contacts to the Ge/GaAs layers and rectifying contacts to the GaAs layer. Damage introduced as a result of the sputtering deposition process is the probable cause of non-ideality in the as-prepared Schottky barriers. However, forward bias current-voltage ideality factors of n = 1.07 have been obtained after annealing.     

Elevated temperature stability of GaAs digital integrated circuits

The elevated temperature stability of a commercial GaAs enhancement-depletion-mode MESFET process has been characterized; the observations made are relevant to device operation at elevated temperatures, with implications for optoelectronic integration on GaAs integrated circuits by selective-area epitaxial growth, and to long term circuit and device reliability. Although the transistor electrical characteristics are stable for up to five hours at 500°C, a metallurgical reaction between the interconnect metal AlCu_x core and WN_x claddings has been identified which limits circuits to five hour operation at 470°C. This later reaction proceeds with an activation energy of 3.5 eV and results in a 15-fold increase in interconnect metal sheet resistance. A geometry-dependent increase in ohmic contact resistance is seen at somewhat higher temperature which is ascribed to the penetration of aluminum-containing compounds to the ohmic contact edge     

采用离子注入N~+层和质子隔离的12GHz 200mW功率GaAs MESFET

本文报导了采用质子隔离和Si~+离子注入N~+接触层技术,提高了功率GaAa MESFET的微波性能和可靠性.已经制成栅长1μm,总栅宽600μm的GaAs功率MESFET,12GHz下最大输出功率210mW,经严格考核表明器件具有较高的可靠性.     

High-temperature stability of refractory-metal VLSI GaAs MESFETs

Commercially available, self-aligned VLSI GaAs MESFETs, with tungsten-based refractory-metal Schottky gates, nickel-based refractory-metal ohmic contacts, and aluminum interconnection metallization, have been thermally cycled and shown to be stable after 3 h at temperatures up to 500°C. Both partially processed and fully processed wafers were found to be stable with no significant change occurring in either Schottky gate or ohmic contact properties. An increase in the channel resistance component of the series resistance is believed to be responsible for I_DS and g_m degradation above 500°C. The fact that commercially available, gold-free VLSI GaAs MESFETs are able to withstand such thermal cycles has very important consequences for monolithic optoelectronic integrated circuit (OEIC) fabrication because it means that it may now be feasible to grow photonic device heterostructures epitaxially on MESFET VLSI wafers; process them into lasers, modulators, and/or detectors; and interconnect them with the electronics to produce VLSI-density OEICs     

GaAs field effect transistors fabricated by imprint lithography

A GaAs metal–semiconductor field-effect transistor (MESFET) has been realized based on mix-and-match fabrication using optical lithography for the ohmic contacts and imprint lithography for the gate. The gate length and width are 1.2 and 80 μm, respectively, the channel length is 4 μm. For the gate definition a Si-mold is embossed into a thin polymer film located on top of an n-doped GaAs layer. The gate is fabricated by metal evaporation and lift-off.