Novel electrical characterization for advanced CMOS gate dielectrics

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks： 1） inelastic electron tunneling spectroscopy （IETS）, 2） lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3） pulse agitated substrate hot electron injection （PASHEI） technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.     

Adaptive H_∞ Control for Nonlinear Hamiltonian Systems with Time Delay and Parametric Uncertainties

This paper addresses the adaptive H∞ control problem for a class of nonlinear Hamiltonian systems with time delay and parametric uncertainties. The uncertainties under consideration are some small parameter perturbations involved in the structure of the Hamiltonian system. Both delay-independent and delay-dependent criteria are established based on the dissipative structural properties of the Hamiltonian systems and the Lyapunov-Krasovskii functional approach. In order to construct the adaptive H∞controller, the situation that the parameter perturbation is inexistent in the system is also studied and the controller is designed.The adaptive H∞ control problem is solved under some sufficient conditions which ensure the asymptotic stability and the L2 gain performance of the resulted closed-loop system. Numerical example is given to illustrate the applicability of the theoretical results.     

Novel devices and process for 32 nm CMOS technology and beyond

The development of next 32 nm generation and below needs innovations on not only device structures, but also fabrication techniques and material selections. Among those promising technologies, new gate structures as high-κ gate dielectric and metal gate, strain channel carrier mobility enhancement technology, and novel non-planar MOSFET structures are all possible candidate technologies. In this paper, we will specify our discussion on the research progress of high-κ-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond.     

Higher-Order Smoothing： A Novel Semantic Smoothing Method for Text Classification

It is known that latent semantic indexing （LSI） takes advantage of implicit higher-order （or latent） structure in the association of terms and documents. Higher-order relations in LSI capture ＂latent semantics＂. These findings have inspired a novel Bayesian framework for classification named Higher-Order Naive Bayes （HONB）, which was introduced previously, that can explicitly make use of these higher-order relations. In this paper, we present a novel semantic smoothing method named Higher-Order Smoothing （HOS） for the Naive Bayes algorithm. HOS is built on a similar graph based data representation of the HONB which allows semantics in higher-order paths to be exploited. We take the concept one step further in HOS and exploit the relationships between instances of different classes. As a result, we move beyond not only instance boundaries, but also class boundaries to exploit the latent information in higher-order paths. This approach improves the parameter estimation when dealing with insufficient labeled data. Results of our extensive experiments demonstrate the value of HOS oi1 several benchmark datasets.     

Novel silicon-controlled rectifier （SCR） for digital and high-voltage ESD power supply clamp

Due to latch-up issue,the main problem of silicon-controlled rectifier(SCR)for power supply clamps in on-chip ESD protection is its inherent low holding voltage,especially in high-voltage applications.In this paper,we proposed a MOS-inside SCR(MISCR)showing nearly no snapback character and good ESD robustness,which is qualified for on-chip power clamp ESD protection.The stacked device achieves a series of triggering and holding voltage by altering the stacking number,which can also be used for the high voltage ESD power supply clamp applications.     

Novel vertical channel double gate structures for high density and low power flash memory applications

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.