Implantation and activation of high concentrations of boron in Germanium

There is renewed interest in the development of Ge-based devices. Implantation and dopant activation are critical process steps for future Ge devices fabrication. Boron is a common p-type dopant, which remarkably is active immediately after implantation in Ge at low doses. This paper examines the effect of increasing dose (i.e., 5/spl times/10/sup 13/-5/spl times/10/sup 16/ cm/sup -2/) and subsequent annealing (400/spl deg/C-800/spl deg/C for 3 h in nitrogen) on activation and diffusion of boron in Ge. Secondary ion mass spectrometry (SIMS), spreading resistance profiling (SRP), high resolution X-ray diffraction (HRXRD), Rutherford backscattering spectrometry (RBS), and nuclear reaction analysis (NRA) are used to characterize the implants before and after annealing. It is found that very high fractions of the boron dose (/spl sim/5%-55%) can be incorporated substitutionally immediately after implantation leading to very high hole concentrations, /spl ges/2/spl times/10/sup 20/ cm/sup -3/, deduced from SRP. Small increases in activation after annealing are observed, however, 100% activation is not indicated by either SRP or NRA. Negligible diffusion after annealing at either 400/spl deg/C or 600/spl deg/C for 3 h was, furthermore, observed.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.     

Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAlP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-/spl mu/m gate lengths exhibit a cutoff frequency (f/sub t/) of 13.7 GHz and a maximum frequency of oscillation (f/sub max/) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8/spl times/10/sup -3/ A/cm/sup 2/ at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the /spl sim/ 11-nm thick native gate oxide.     

Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0/spl times/10/sup -6/ C/cm/sup 2/) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1/spl times/10/sup -6/ C/cm/sup 2/) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level.     

Poly-Si TFT Fabricated at 150 deg C Using ICP-CVD and Excimer Laser Annealing

We fabricated poly-Si thin-film transistors at 150/spl deg/C using inductively coupled plasma (ICP) chemical vapor deposition (CVD) and excimer laser annealing (ELA). An Si film deposited by ICP-CVD was recrystallized using ELA, and a poly-Si film with large grains exceeding 5000 /spl Aring/ in diameter was fabricated. An SiO/sub 2/ film with a high breakdown field was deposited by ICP-CVD. A high mobility exceeding 100 cm/sup 2//Vs and a low subthreshold swing of 0.76 V/dec were successfully achieved.     

A 4.15 kV 9.07-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC Schottky-barrier diode using Mo contact annealed at high temperature

In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-/spl Aring/ gate dielectrics

This letter reports the observation of a process integration issue that arises when large doses of nitrogen (>1/spl times/10/sup 15/ cm/sup -2/) are incorporated in oxynitride gate dielectric films targeting equivalent oxide thickness of 11-13 /spl Aring/. It is shown that capacitance-extracted active doping density at the polysilicon/oxynitride (poly/SiON) interface of boron-doped p/sup +/-polysilicon gated pMOSFETs decreases with increasing nitrogen dose of the oxynitride film as measured by X-ray photoelectron spectroscopy. A physical mechanism is proposed to explain experimental observations.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Film Properties of MoSi/sub 2/ and Their Application to Self-Aligned MoSi/sub 2/ Gate MOSFET

Molybdenum silicide (MoSi/sub 2/) gate technology has been extensively investigated in conjunction with MOS device performance and reliability. Features of the MoSi/sub 2/) gate technology are to realize a low resistivity of 1 X 10/sup -4/ Omega · cm for both gate and interconnection, and to give rise to higher reliability under both positive and negative bias stress of 2 MV/cm at 250/spl deg/C. Problems on the ohmic contact between MoSi/sub 2/ and single-crystal substrates are not completely solved yet, particularly when the device is processed at high temperature after MoSi/sub 2/ deposition.     

Boron retarded diffusion in the presence of indium or germanium

Experimental results of germanium (Ge) and indium (In) preamorphization by ion-implantation show that the diffusion of boron (B) is retarded by the presence of Ge or In and that this retardation is more important than the preamorphization (dechanneling) effect. Result shows that In retards B diffusion more than Ge and the retardation effect due to In becomes greater with increasing retained dose of In. Larger In doses cause larger strain, which results in more B being tied up in immobile clusters near the surface. In order to achieve adequate retained dose of In, the implanted dose of In must be increased to 5/spl times/10/sup 15/ cm/sup -2/. After anneal, the junction depth (at 10/sup 18/ cm/sup -3/) is reduced from 628 /spl Aring/ in the control wafer (no In co-implant) to 480 /spl Aring/.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

30-GHz-band over 5-W power performance of short-channel AlGaN/GaN heterojunction FETs

This paper describes the small-signal characterization through delay-time analysis and high-power operation of the Ka-band of AlGaN/GaN heterojunction field-effect transistors (FETs). An FET with a gatewidth of 100 /spl mu/m and a gate length of 0.09 /spl mu/m has exhibited a current gain cutoff frequency (f/sub T/) of 81 GHz, a maximum frequency of oscillation (fmax) of 187 GHz, and a maximum stable gain of 10.5 dB at 30 GHz (8.3 dB at 60 GHz). Delay-time analysis has demonstrated channel electron velocities of 1.50/spl times/10/sup 7/ to 1.75/spl times/10/sup 7/ cm/s in a gate-length range of 0.09-0.25 /spl mu/m. State-of-the-art performance-saturated power of 5.8 W with a linear gain of 9.2 dB and a power-added efficiency of 43.2%-has been achieved at 30 GHz using a single chip having a gatewidth of 1.0 mm and a gate length of 0.25 /spl mu/m.     

Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 /spl mu/m /spl sim/4.9/spl times/10/sup 14/ cm/sup -3/-doped drift layer. Blocking voltages (V/sub B/) of 10 kV to 11 kV have been measured. The best specific on-resistance (R/sub SP/_/sub ON/) normalized to source active area has been determined to be 130 m/spl Omega//spl middot/cm/sup 2/. Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 m/spl Omega//spl middot/cm/sup 2/ if it is scaled up substantially in size.     

Modeling of boron and phosphorus implantation into (100) Germanium

Boron and phosphorus implants into germanium and silicon with energies from 20 to 320 keV and ion doses from 5/spl times/10/sup 13/ to 5/spl times/10/sup 16/ cm/sup -2/ were characterized using secondary ion mass spectrometry. The first four moments of all implants were calculated from the experimental data. Both the phosphorus and boron implants were found to be shallower in the germanium than in the silicon for the same implant parameters and high hole concentrations, as high as 2/spl times/10/sup 20/ cm/sup -3/, were detected by spreading resistance profiling immediately after boron implants without subsequent annealing. Channeling experiments using nuclear reaction analysis also indicated high substitutional fractions (/spl sim/19%) even in the highest dose case immediately after implant. A greater straggle (second moment) is, however, observed in the boron implants in the germanium than in the silicon despite having a shorter projected range in the germanium. Implant profiles predicted by Monte Carlo simulations and Lindhard-Scharff-Schiott theory were calculated to help clarify the implant behavior. Finally, the experimentally obtained moments were used to calculate Pearson distribution fits to the boron and phosphorus implants for rapid simulation of nonamorphizing doses over the entire energy range examined.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献