A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.     

Low standby power state storage for sub-130-nm technologies

Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.     

A poly-Si TFT fabricated by excimer laser recrystallization onfloating active structure

This letter reports a. new excimer laser annealing (ELA) method to produce large polycrystalline silicon (poly-Si) lateral grains exceeding 4 μm. A selectively floating amorphous silicon (a-Si) flint with a 50 nm-thick air-gap was irradiated by a single-pulse XeCl excimer laser and uniform lateral grains were grown due to the lateral thermal gradient caused by the low thermal conductivity of the air. A poly-Si thin-film transistor (TFT) with two high-quality 4.6 μm-long lateral grains was fabricated by employing the proposed ELA and high field-effect mobility of 331 cm²/Vsec was obtained due to. the high-quality grain structure     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

Characteristics of sub-1/4-μm gate surface channel PMOSFET'susing a multilayer gate structure of boron-doped poly-Si on thinnitrogen-doped poly-Si

This paper reports the effects of a new p⁺ gate structure (MBN gate) on the properties of surface channel PMOSFET's with an extremely thin gate oxide. The MBN gate is a multilayer gate structure of boron-doped poly Si on thin nitrogen-doped poly-Si. The thin nitrogen-doped Si layer effectively suppresses boron diffusion, so that the gate poly Si can be doped with boron in high concentration without the fear of boron penetration. Gate depletion effects are well suppressed. Effective hole mobility is improved due to the reduction of the initial interface state density. The hot-hole induced interface state generation is shown to be the dominant clause of degradation in the 1/4-μm level PMOSFET's, and less Gm degradation is found in the MBN-gate PMOSFET's than in conventional p⁺-gate PMOSFET's. Finally, with respect to the reliability of the gate oxide, a conventional p⁺ gate with boron penetration exhibits an increase in short-time defect related breakdown during constant-current FN stressing. Short-time defect-related breakdown is not observed in the MBN gate but a slight decrease in charge to breakdown     

非晶硅薄膜的准分子激光晶化研究

利用Kr准分子激光器晶化非晶硅薄膜, 研究了不同的激光能量密度和脉冲次数对非晶硅薄膜晶化效果的影响.利用X 射线衍射(XRD)和扫描电子显微镜(SEM)对晶化前后的样品的物相结构和表面形貌进行了表征和分析.实验结果表明, 在激光频率为1 Hz 的条件下, 能量密度约为180 mJ/cm2时,准分子激光退火处理实现了薄膜由非晶结构向多晶结构的转变;当大于晶化阈值180 mJ/cm2小于能量密度230 mJ/cm2时, 随着激光能量密度增大, 薄膜晶化效果越来越好;激光能量密度为230 mJ/cm2时, 晶化效果最好、晶粒尺寸最大, 约60 nm, 并且此时薄膜沿Si(111)面择优生长;脉冲次数50 次以后对晶化的影响不大.     

High-performance poly-Si TFTs made by Ni-mediated crystallization through low-shot laser annealing

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been fabricated using metal-induced crystallization followed by laser annealing (L-MIC). Laser annealing after MIC was found to yield a major improvement to the electrical characteristics of poly-Si TFTs. At a laser fluence of 330 mJ/cm/sup 2/, the field effect mobility increased from 71 to 239 cm/sup 2//Vs, and the minimum leakage current reduced from around 3.0/spl times/10/sup -12/ A//spl mu/m to 2.9/spl times/10/sup -13/ A//spl mu/m at a drain voltage of 5 V. In addition, the dependence of the TFT characteristics on the laser energy density was much weaker than that for conventional excimer laser annealed poly-Si TFTs.     

Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, V/sub DD/, temperature, and local and global threshold variation. The V/sub T/ variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution.     

Ultrashallow junction formation by self-limiting LTP and its application to sub-65-nm node MOSFETs

We have developed a novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way. Key technology is realized by introducing a new process combination of preamorphization implantation and a heat absorber with a phase switch layer, and by optimizing them. The V/sub th/ rolloffs of MOSFETs formed by this method were remarkably improved compared to those by rapid thermal annealing when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate complementary metal-oxide semiconductor devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.     

A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.     

A new method for the channel-length extraction in MOSFETs with sub-2-nm gate oxide

A simple method to extract the effective channel length in deep-submicrometer devices with sub-2-nm gate oxide thickness is presented. The method uses the measured gate current from accumulation to strong inversion. It is easy to implement, fast, and accurate.     

The investigation of key technologies for sub-0.1-μm CMOS devicefabrication

The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p⁺/n⁺ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved     

65-nm CMOS Voltage-to-Time Converter for 5-GS/s Time-Based ADCs

This paper discusses a voltage-to-time converter (VTC) designed for use in a time-based analog-to-digital converter. The VTC considered in this work is based on a starved-inverter topology. Linearity, delay, and jitter of the VTC are analyzed to facilitate a physical understanding of the circuit performance. The design is experimentally verified in a 65-nm CMOS technology. Measurement results show that the VTC, operating with a 5-GHz clock, has an output delay range of \(\pm 25\,{\text{ ps }}\), 4.4 effective number of bits (ENOB), and output jitter of \(0.5\,\text{ ps }\) RMS while consuming 4 mW of power. The input effective resolution bandwidth (ERBW) of the VTC is measured to be 4.1 GHz, over which the ENOB remains above 3.5 bits. The same VTC, operating with a 7.5-GHz clock, consumes 9.7 mW of power from a 1.2-V supply, has ENOB of >3.8 bits, ERBW of >7 GHz, output jitter of \(0.4\,\text{ ps }\) RMS, and output delay range of \(\pm 25\,\text{ ps }\). The VTC achieves the widest input bandwidth of any VTC reported to date.     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.     

Nickel silicide contacts formed by excimer laser annealing for high efficiency solar cells

Driven by the relatively high cost of silver (Ag), interest has grown in the photovoltaic (PV) industry to substitute conventional screen printed (SP) Ag front contacts with copper (Cu) plated contacts. The approach chosen here applies selective laser ablation of the front anti‐reflection coating (ARC), then forming self‐aligned nickel silicides (NiSi_x) contacts, and thickening the lines by Cu plating to achieve the desired line conductivity. A successful implementation of this scheme requires annealing to form NiSi_x with low contact resistance. However, it has been shown that industrial shallow emitters can be damaged severely upon conventional annealing of nickel. In this paper, we show that by using large area excimer laser annealing (ELA), NiSi_x contacts can be formed on industrial shallow emitters without the associated junction degradation. On the basis of sheet resistance, transmission electron microscopy, and lifetime measurements, we demonstrate that NiSi_x formation by ELA can be achieved in narrow contact openings without damaging the passivation and reflectance properties of the neighboring ARC. In addition, the thresholds for NiSi_x formation for different Ni thicknesses are quantified by rigorous finite element simulations and compared with experimental data. Finally, high efficiency passivated emitter and rear cell type solar cells featuring a shallow 85 Ω/sq emitter have been processed on large area CZ–Si using laser ablation of the ARC and subsequent NiSi_x formation by ELA. These cells show an average efficiency gain of 0.4%_abs compared with cells processed with reference SP contacts. In this work, the best performing cell with the ELA process reached 20.0% energy conversion efficiency. Copyright © 2013 John Wiley & Sons, Ltd.     

Effect of UV/VUV enhanced RTP on process variation and device performance of metal gate/high-/spl kappa/ gate stacks for the sub-90-nm CMOS regime

We show that UV/VUV-enhanced rapid thermal processing (RTP) in combination with single-wafer processing using a single tool for the fabrication of metal gate/high-/spl kappa/ dielectric gate stacks not only improves overall device performance, but also leads to a significant reduction in process variation at the front end of the CMOS process flow for the sub-90-nm technology node. The gate stacks were fabricated under various UV/VUV conditions. Gate stacks processed under UV/VUV radiation during all processing steps displayed low leakage currents of the order of 10/sup -11/ A/cm/sup 2/. It is shown that the Al-Al/sub 2/O/sub 3/-Si gate stacks processed under UV/VUV conditions also display the lowest variations both in mean leakage current and mean capacitance, as compared to devices where UV/VUV was not used for all the processing steps. Therefore, it can be see that reliance on successive corrective iterations common to automatic process control or standard design simulation can be reduced significantly. As a result, UV/VUV-enhanced RTP has the potential to reduce the effect of process variations on overall device performance, thereby making the overall process more cost effective and time efficient and therefore improving yield and device reliability.     

Analytic model for the post-breakdown conductance of sub-5-nm SiO/sub 2/ gate oxides

A new model for the post-breakdown conductance of ultrathin gate oxides based on the generalized diode equation is presented. The model is expressed in terms of the Lambert W function, that is, the inverse of the function w/spl rarr/we/sup w/. We show that this alternative formulation improves a previous one, the quantum point contact model, especially in the low bias range, where the role played by the semiconductor electrodes cannot be overlooked. The practical implementation of the proposed equations is discussed.